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4:4 Differential-to-LVPECL/LVDS Clock Multiplexer

パッケージ情報

CADモデル:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG24
Lead Count (#):24
Pkg. Dimensions (mm):7.8 x 4.4 x 1.0
Pitch (mm):0.65

環境及び輸出分類情報

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

製品スペック

Lead Count (#)24
Carrier TypeReel
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)3000
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Additive Phase Jitter Typ RMS (fs)220
Additive Phase Jitter Typ RMS (ps)0.22
Adjustable PhaseNo
Advanced FeaturesUniversal outputs
Channels (#)1
Core Voltage (V)2.5V, 3.3V
FunctionBuffer, Multiplexer
Input Freq (MHz)3000
Input TypeCML, LVDS, LVPECL
Inputs (#)4
Length (mm)7.8
MOQ3000
Output Banks (#)1
Output Freq Range (MHz)3000
Output Skew (ps)25
Output TypeLVDS, LVPECL
Output Voltage (V)2.5V, 3.3V
Outputs (#)4
Package Area (mm²)34.3
Pitch (mm)0.65
Pkg. Dimensions (mm)7.8 x 4.4 x 1.0
Pkg. TypeTSSOP
Product CategoryClock Buffers & Drivers, Clock Multiplexers, RF Buffers
Prog. InterfacePin select
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)2.5 - 2.5, 3.3 - 3.3
Tape & ReelYes
Thickness (mm)1
Width (mm)4.4

説明

The 859S0424I is a 4:4 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The outputs for this device can either be programmed to give LVPECL or LVDS levels. The 859S0424I has four selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.