特長
- Five differential LVDS or LVPECL outputs
- Two differential clock input pairs
- CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
- PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL
- Either CLK or PCLK inputs can be configured to accept single-ended inputs
- Maximum output frequency: >2GHz
- Output skew: 25ps (typical)
- Propagation delay: 575ps (typical)
- Full 3.3V or 2.5V power supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
854S015I-01 - Block Diagram
説明
The 854S015-01 is a low skew, high performance 1-to-5, 2.5V, 3.3V Differential-to-LVPECL/ LVDS Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The 854S015-01 has two selectable differential clock inputs. Guaranteed output and part-to-part skew characteristics make the 854S015-01 ideal for those applications demanding well defined performance and repeatability.
