特長
- Five differential 2.5V/3.3V LVPECL outputs
- Selectable differential CLKx, nCLKx inputs
- CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
- Maximum output frequency: 700MHz
- Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input
- Output skew: 30ps (maximum)
- Propagation delay: 1.8ns (maximum)
- RMS phase jitter @ 155.52MHz (12kHz - 20MHz): 0.05ps (typical)
- LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
85314I-11 - Block Diagram
説明
The 85314I-11 is a low skew, high performance 1-to-5 Differential-to-2.5V/3.3V LVPECL fanout buffer. The 85314I-11 has two selectable differential clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85314I-11 ideal for those applications demanding well defined performance and repeatability.
