パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.5 |
環境及び輸出分類情報
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
製品スペック
| Pkg. Type | VFQFPN |
| Lead Count (#) | 32 |
| Pb (Lead) Free | Yes |
| Carrier Type | Reel |
| Advanced Features | VCXO-based APLL |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 0.008 - 156.25 |
| Input Type | LVPECL, LVDS, HCSL, HSTL |
| Inputs (#) | 2 |
| Length (mm) | 5 |
| Loop Bandwidth Range (Hz) | 15 - 60 |
| MOQ | 2500 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 19.44 - 622.08 |
| Output Skew (ps) | 50 |
| Output Type | LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 25 |
| Pb Free Category | e3 Sn |
| Phase Jitter Max RMS (ps) | 0.736 |
| Phase Jitter Typ RMS (ps) | 0.616 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 0 |
| Qty. per Reel (#) | 2500 |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
| Xtal Freq (KHz) | 27000 - 27000 |
| 掲載 | No |
813N322-02 に関するリソース
説明
The 813N322-02 device uses Renesas' fourth-generation FemtoClock® NG technology for optimal high clock frequency and low phase noise performance, combined with low power consumption and high power supply noise rejection. The 813N322-02 is a PLL-based synchronous multiplier that is optimized for Ethernet to SONET/PDH clock jitter attenuation and frequency translation.
The 813N322-02 is a fully integrated phase-locked loop (PLL) utilizing a FemtoClock NG digital VCXO that provides the low jitter, high-frequency SONET/PDH output clock that easily meets OC-48 jitter requirements. This VCXO technology simplifies PLL design by replacing the pullable crystal requirement of analog VCXOs with a fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is provided by an external loop filter. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support the most common clock rates used in PDH, SONET, and Ethernet applications. The device requires the use of an external, inexpensive fundamental mode 27MHz crystal. The device is packaged in a space-saving 32-VFQFN package and supports the industrial temperature range.