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ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
FemtoClock® Jitter Attenuator & Multiplier Frequency Translator W/LVPECL Outputs

パッケージ情報

Pkg. Type:TSSOP
Pkg. Code:PGG24
Lead Count (#):24
Pkg. Dimensions (mm):7.8 x 4.4 x 1.0
Pitch (mm):0.65

環境及び輸出分類情報

Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090
Moisture Sensitivity Level (MSL)1

製品スペック

Pkg. TypeTSSOP
Lead Count (#)24
Pb (Lead) FreeYes
Carrier TypeReel
Advanced FeaturesVCXO-based APLL
App Jitter CompliancePCIe
C-C Jitter Max P-P (ps)20
Core Voltage (V)3.3
Feedback InputNo
Input Freq (MHz)19.6 - 27.2, 49 - 68, 78.4 - 136
Input TypeLVPECL, LVDS, HCSL, HSTL
Inputs (#)1
Length (mm)7.8
Loop Bandwidth Range (Hz)100 - 400
MOQ2500
Moisture Sensitivity Level (MSL)1
Output Banks (#)1
Output Freq Range (MHz)19.6 - 27.2, 98 - 170, 245 - 340
Output Skew (ps)35
Output TypeLVPECL
Output Voltage (V)2.5V, 3.3V
Outputs (#)3
Package Area (mm²)34.3
Pb Free Categorye3 Sn
Period Jitter Max P-P (ps)3.25
Period Jitter Typ P-P (ps)2.5
Phase Jitter Typ RMS (ps)0.421
Pitch (mm)0.65
Pkg. Dimensions (mm)7.8 x 4.4 x 1.0
Prog. ClockNo
Qty. per Carrier (#)0
Qty. per Reel (#)3000
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Temp. Range (°C)0 to 70°C
Thickness (mm)1
Width (mm)4.4
Xtal Freq (KHz)20000 - 25000

説明

The 813253 is a PLL based synchronous clock generator that is optimized for Gigabit Ethernet and PCI Express®™ clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock® frequency multiplier that provides the low jitter, high frequency Gigabit Ethernet or PCI Express®™ output clock. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in Gigabit Ethernet and PCI Express® applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics.