特長
- Clock frequencies up to 100 MHz (6.5ns access time)
- Select IDT Standard timing or First Word Fall Through Timing
- Programmable Almost-Empty and Almost-Full flags
- each has five
- default offsets (8, 16, 64, 256 and 1,024 )
- Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)
- Retransmit Capability
- Free-running CLKA and CLKB may be asynchronous or coincident
- Auto power down minimizes power dissipation
- Available in 128-pin TQFP package
- Pin compatible to the lower density parts IDT72V36x4
- Industrial temperature range (–40C to +85C) is available
72V3664 - Block Diagram
説明
The 72V3664 is a 3.3V bidirectional synchronous (clocked) FIFO. Two independent 4K x 36 dualport SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
