特長
- Pin-compatible with the 72V2x1and 72V21x1 SuperSync FIFOs
- Functionally compatible with the 5 Volt 72261
- 10ns read/write cycle time (6.5ns access time)
- Fixed, low first word data latency time
- 5V input tolerant
- Auto power down minimizes standby power consumption
- Retransmit operation with fixed, low first word data latency time
- Empty, Full and Half-Full flags signal FIFO status
- Programmable Almost-Empty and Almost-Full flags
- Easily expandable in depth and width
- Independent Read and Write clocks (permit reading and writing simultaneously)
- Available in the 64-pin TQFP and STQFP packages
- Industrial temperature range (–40C to +85C) is available
72V261 - Block Diagram
説明
The 72V261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72261 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)
パラメータ
| 属性 | 値 |
|---|---|
| Core Voltage (V) | 3.3 |
| Bus Width (bits) | 9 |
| Density (Kb) | 144 |
| Pkg. Code | PPG64 |
| Interface | Synchronous |
| I/O Type | 3.3 V LVTTL |
| I/O Frequency (MHz) | 100 - 100 |
| Organization | 16K x 9 |
| Temp. Range (°C) | 0 to 70°C |
| Architecture | Uni-directional |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TQFP | 10.0 x 10.0 x 1.4 | 64 | 0.5 |
