特長
- Clock frequencies up to 83 MHz (8ns access time)
- Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports
- 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word)
- Programmable Almost-Empty and Almost-Full flags
- Serial or parallel programming of partial flags
- Loopback mode on Port A
- Retransmit Capability
- Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
- Mailbox bypass registers for each FIFO
- Free-running CLKA, CLKB and CLKC may be asynchronous or coincident
- Auto power down minimizes power dissipation
- Available in 128-pin TQFP package
- Pin compatible to the lower density parts, 7236x6
- Industrial temperature range (–40C to +85C) is available
723656 - Block Diagram
説明
The 723656 is a 2K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode.
