概要
説明
The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
特長
- Free-running CLKA and CLKB may be asynchronous or coincident
- Two independent clocked FIFOs buffering data in opposite directions
- Mailbox bypass register for each FIFO
- Programmable Almost-Full and Almost-Empty flags
- Supports clock frequencies up to 83MHz
- Fast access times of 8ns
- Available in 120-pin TQFP package
- Industrial temperature range (–40C to +85C) is available
