特長
- Dual-port allows simultaneous access of the same memory location
- Selectable Pipelined or Flow-Through Output mode
- Counter Enable and Repeat features
- Interrupt flags
- Full synchronous operation on both ports
- Separate byte controls for multiplexed bus and bus-matching compatibility
- Dual Cycle Deselect (DCD) for Pipelined Output mode
- 2.5V (±100mV) power supply for core
- LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port
- Includes JTAG functionality
- Available in a 256-pin BGA
- Common BGA footprint provides design flexibility over seven density generations (512K to 36M-bit)
- Industrial temperature range (-40 °C to +85 °C) is available
70T3509M - Block Diagram
説明
The 70T3509M is a high-speed 1024K x 36-bit synchronous dual-port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power-down feature, controlled by the Chip Enable (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3509M can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.
パラメータ
| 属性 | 値 |
|---|---|
| Core Voltage (V) | 2.5 |
| Bus Width (bits) | 36 |
| Density (Kb) | 36864 |
| Pkg. Code | BPG256 |
| Interface | Sync |
| I/O Type | 2.5 V LVTTL, 3.3 V LVTTL |
| I/O Frequency (MHz) | 133 - 133 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Dual-Port |
| Organization | 1024K x 36 |
| Function | Interrupt, Sleep Mode |
| Output Type | Flowthrough, Pipelined |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| CABGA | 17.0 x 17.0 x 1.76 | 256 | 1 |
