特長
- Packaged as 28 pin SSOP, Pb free (150 mil body)
- Synchronizes fractional clocks rising edges
- CMOS in to PECL out
- Pin selectable dividers
- Zero input to output skew
- User determines the output frequency - no software needed
- Slices frequency or period
- Input clock frequency of 1.5 MHz to 200 MHz
- Output clock frequencies from 2.5 MHz to 160 MHz
- Very low jitter
- Duty cycle of 45/55
- Operating voltage of 3.3 V
- Advanced, low power CMOS process
527-03 - Block Diagram
説明
The 527-03 is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The 527-03 aligns rising edges on CLKIN with FBPECL at a ratio determined by the reference and feedback dividers. For a PECL input and output clock with zero delay, use the 527-04.
