特長
- Phase-locked loop clock distribution
- 10MHz to 133MHz operating frequency
- Distributes one clock input to one bank of five and one bank of four outputs
- Separate Output Enable for each output bank
- Output Skew < 250ps
- Low jitter <200ps cycle-to-cycle
- 23S09-1 for standard drive
- 23S09-1H for high drive
- No external RC network is required
- Operates at 3.3V VDD
- Spread spectrum compatible
- Available in SOIC and TSSOP packages
説明
The 23S09 is a high-speed phase-locked loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10MHz to 133MHz. The device is a 16-pin version of the 23S05.
The 23S09 accepts one reference input and drives two banks of four low-skew clocks. The -1H version of this device operates up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the 23S09 enters power down. In this mode, the device will draw less than 12μA for the commercial temperature range and less than 25μA for the industrial temperature range, and the outputs are tri-stated. This device is characterized for both industrial and commercial operation.
パラメータ
| 属性 | 値 |
|---|---|
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Product Category | Zero Delay Buffers |