特長
- Phase-Lock Loop Clock Distribution
- 10MHz to 133MHz operating frequency
- Distributes one clock input to one bank of five and one bank of four outputs
- Separate output enable for each output bank
- Output Skew < 250ps
- Low jitter <175 ps cycle-to-cycle
- 50ps typical cycle-to-cycle jitter (15pF, 66MHz)
- IDT2309B-1 for Standard Drive
- IDT2309B-1H for High Drive
- No external RC network required
- Operates at 3.3V VDD
- Available in SOIC and TSSOP packages
説明
The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309B is a 16-pin version of the IDT2305B. The IDT2309B accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates at up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2309B enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25?A. The IDT2309B is characterized for both Industrial and Commercial operation.
