特長
- Phase-lock loop clock distribution
- 10MHz to 133MHz operating frequency
- Distributes one clock input to one bank of five outputs
- Zero input-output delay
- Output skew < 250ps
- Low jitter <175ps cycle-to-cycle
- 50ps typical cycle-to-cycle jitter (15pF, 66MHz)
- 2305B-1 for standard drive
- 2305B-1H for high drive
- No external RC network required
- Operates at 3.3V VDD
- Power down mode
- Available in SOIC and TSSOP packages
説明
The 2305B is a high-speed phase-locked loop (PLL) clock buffer designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10MHz to 133MHz. The 2305B is an 8-pin version of the 2309B. This device accepts one reference input and drives out five low-skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the 2305B enters power down. In this mode, the device will draw less than 25μA, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power. The 2305B is characterized for both industrial and commercial operation.
パラメータ
| 属性 | 値 |
|---|---|
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Product Category | Zero Delay Buffers |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| SOIC | 4.9 x 3.9 x 1.5 | 8 | 1.27 |
