概要
説明
This is the evaluation kit for the RC32508A jitter attenuator and clock generator. The board comes populated with an RC32508A device.
特長
- Can be configured as clock generator or jitter attenuator/synchronizer
- Low power, less than 0.8W typical
- Low jitter, less than 50fs-RMS
- Compliant with ITU-T G.8262 & G.8262.1 option 1 and 2 for synchronous Ethernet Equipment Clock (EEC/eEEC) without degrading output jitter
- Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz
- Up to 2 independent frequency domains and 8 integer output dividers
- Each frequency domain can be slaved with DPLL or free-run
- DPLL can be configured as DCO
- LVCMOS, AC-LVPECL, AC-LVDS, HCSL, AC-CML output modes supported with programmable output swing
- Up to 2single ended or 1differential clock inputs, 1 crystal/XO/TCXO/OCXO input
- Supports 1MHz I2C, 400kHz SMBus or 50MHz SPI serial port
- Internal non-volatile memory (up to 8 different configurations) provides default device settings on power-up.
- 1.8V core and output operation
- -40°C to +85°C industrial temperature operation
アプリケーション
設計・開発
サポート
ビデオ&トレーニング
Demonstration of Renesas’ Lab on the Cloud virtual environment for FemtoClock®2 ultra-low phase noise synthesizer and jitter attenuator.