特長
- 28-bit 1:2 registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- Supports LVCMOS switching levels on CSGateEN and RESET inputs
- Low voltage operation: VDD = 1.7V to 1.9V
説明
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.
適用されたフィルター
読込中