The 82P33714 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) provides tools to manage timing references, clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33714 meets the requirements of ITU-T G.8262 for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces. For 10G-40G SyncE single-board applications, see the 82P33731

IDT’s third generation Universal Frequency Translator family also includes the 8T49N285 (2-in / 1-PLL / 8-out), 8T49N286 (4-in / 2-PLL / 8-out), and 8T49N287 (2-in / 2-PLL / 8-out), and the 8T49N242 (2-in / 1-PLL / 4-out).

► Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper

特長

  • Complies with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • DPLLs lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI/OBSAI and GNSS frequencies using fractional-N input dividers
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings
  • Prevents output frequency corruption due to a bad PHY reference by accepting Loss of Signal (LOS) inputs from PHYs that immediately disqualify a reference
  • DPLL1 can be configured as a DCO (Digitally Controlled Oscillator) to support IEEE 1588 based clock generation under external processor control
  • Supports network timing master applications by locking to 1 PPS (Pulse Per Second) references from GPS or other GNSS sources
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 72 pin QFN package

descriptionドキュメント

タイトル language 分類 形式 サイズ 日付
データシート
star 82P33714 Datasheet データシート PDF 1.19 MB
アプリケーションノート、ホワイトペーパー
AN-807 Recommended Crystal Oscillators for Network Synchronization アプリケーションノート PDF 148 KB
IDT Products for Wired Broadband Applications Application Brief PDF 686 KB
AN-890 SETS for IEEE 1588 and Synchronous Ethernet 82P337xx Register Map アプリケーションノート PDF 752 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment アプリケーションノート PDF 324 KB
AN-861 Recommended Crystals for IDT VCXO-based Synchronization PLLs アプリケーションノート PDF 300 KB
AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx アプリケーションノート PDF 249 KB
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-901 How to Implement Master/Slave for SETS and SMU Devices on Timing Redundancy Designs アプリケーションノート PDF 606 KB
AN-865 8T49N285_6_7 Frequency Synchronization Compliance Report アプリケーションノート PDF 1.13 MB
ITU-T Profiles for IEEE 1588 ホワイトペーパー PDF 1.17 MB
AN-893 8T49N241_2 Frequency Synchronization Compliance Report アプリケーションノート PDF 1.11 MB
AN-871 Generating SyncE Line Cards Using IDT UFT3G アプリケーションノート PDF 777 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations アプリケーションノート PDF 115 KB
AN-839 RMS Phase Jitter アプリケーションノート PDF 233 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-801 Crystal-High Drive Level アプリケーションノート PDF 202 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
AN-806 Power Supply Noise Rejection アプリケーションノート PDF 438 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 製品変更通知 PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 製品変更通知 PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
PCN# : N1412-01 Die revision change 82P33814, 82P33831, 82P33714, 82P33731, 82P33810 製品変更通知 PDF 40 KB
その他資料
IDT Clock Generation Overview 概要 PDF 1.83 MB
Timing Fabric for Communications Equipment Overview 概要 PDF 263 KB

file_downloadダウンロード

タイトル language 分類 形式 サイズ 日付
ソフトウェア
Timing Commander Installer (v1.17) ソフトウェア/ツール-その他 ZIP 18.02 MB
82P33xx4 Timing Commander Personality ソフトウェア/ツール-その他 TCP 3.50 MB

memoryボード&キット

製品名 タイトル 分類 会社名
82EBP33814 Evaluation Board for 82P33814 Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet Evaluation Renesas