Warning message
Features
- 4 - 0.7 V HCSL differential output pairs
- Supports Serial-ATA at 100 MHz
- Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread
- Unused inputs may be disabled in either driven or Hi-Z state for power management
- M/N Programming
Description
The 9FG104 is a Synthesizer that provides 4 differential output pairs that are compliant to the Intel CK410 specification. It also provides support for PCI-Express and SATA. The part synthesizes several output frequencies from either a 14.31818 MHz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to-output skew of less than 35 ps. Generates common CPU frequencies from 14.318 MHz or 25 MHz Crystal or reference input
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 4 |
| Diff. Output Signaling | HCSL |
| Output Freq Range (MHz) | 100 - 400 |
| Power Consumption Typ (mW) | 360, 363 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | HCSL, LVCMOS |
| Xtal Freq (MHz) | 14.318 - 14.318, 25 - 27 |
| Diff. Termination Resistors | 16 |
| Package Area (mm²) | 42.7, 54.1 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Input Freq (MHz) | 14.318 - 14.318, 25 - 27 |
| Input Type | Crystal, LVCMOS |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 0.8V, 3.3V |
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Simulation Models
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.