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Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

93732

Obsolete

DDR Zero Delay Clock Buffer

Features

  • Low skew, low jitter PLL clock driver
  • Max frequency supported = 266MHz (DDR 533)
  • I2C for functional and output control
  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • 3.3V tolerant CLK_INT input
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Description

DDR Zero Delay Clock Buffer

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