Features
- AEC-Q101 qualified GaN technology
- Dynamic RDS(on)eff production tested
- Robust design, defined by
- Intrinsic lifetime tests
- Wide gate safety margin
- Transient over-voltage capability
- Enhanced inrush current capability
- Very low QRR
- Reduced crossover loss
- Enables AC-DC bridgeless totem-pole PFC designs
- Increased power density
- Reduced system size and weight
- Overall lower system cost
- Achieves increased efficiency in both hard- and soft-switched circuits
- Easy to drive with commonly-used gate drivers
- GSD pin layout improves high speed design
- RoHS-compliant and Halogen-free packaging
TP65H035G4WSQA Typical Diagram
Description
The TP65H035G4WSQA 650V 35mΩ Gallium Nitride (GaN) FET is a normally-off device built using our GenIV platform. Using proprietary technology, resulting in reduced internal package inductance and a simplified assembly process. It combines a state-of-the-art high voltage GaN HEMT with a low voltage silicon MOSFET to offer superior reliability and performance. The device is also automotive-qualified to 175°C, having passed the AEC-Q101 stress tests for automotive-grade discrete semiconductors.
Renesas' GaN power products offer improved efficiency over silicon through lower gate charge, lower crossover loss, and smaller reverse recovery charge.
The TP65H035G4WSQA is offered in an industry-standard 3-lead TO-247 with a common source package configuration.
Applications
- Automotive
- Datacom
- Broad industrial
- PV inverter
- Servo motor
| Part Number | Status | Samples | Stock | Package | Carrier Type | Moisture Sensitivity Level (MSL) | Mounting Type | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|
| TP65H035G4WSQA | NRND | N/A | In Stock | TO-247 | Tube | 3 | Through Hole | -55 to +150°C |
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- White PaperPDF 1.9 MB R16WP0012EU0100 Rev.1.00 Dec 19, 2025D-Mode GaN combines the best of both GaN and Silicon and is ideal for high-voltage applications with high-speed, high-voltage GaN switching, robust 4V threshold gate compatible with standard gate drivers, and a range of standard package offerings not available with other GaN technologies.
- Technical BriefPDF 992 KB R16TB0004EU0100 Rev.1.00 Dec 02, 2025
- Application NotePDF 372 KB Dec 11, 2024AI-generated Summary: GaN power switches require careful PCB layout and probing techniques to fully utilize their fast switching capabilities. Minimizing parasitic inductances and capacitances in the power and gate drive loops reduces ringing and ensures stable operation. A large ground plane, close placement of power components, and short, wide traces in the gate drive circuit improve performance. Accurate probing demands short ground leads and direct probe placement to avoid measurement artifacts. Avoid adding parasitics during probing by using floating oscilloscopes and minimizing wire lengths. The document also highlights the importance of proper decoupling and grounding strategies for high-frequency switching circuits.
- Application NotePDF 380 KB Dec 11, 2024AI-generated Summary: Renesas GaN Power Switches combine a normally-off low voltage Si MOSFET and a normally-on high voltage GaN HEMT in a cascode configuration, enabling ultra-fast switching with low reverse recovery charge. This design minimizes switching losses and improves reverse conduction performance compared to traditional silicon MOSFETs. The GaN switch operates in three modes: forward blocking, forward conduction, and reverse conduction, with significantly reduced reverse recovery charge and time, enhancing efficiency in power applications. Reverse recovery tests show the GaN switch has 25 times lower recovery charge than comparable CoolMOS devices, demonstrating superior performance.
- GuidePDF 225 KB Jul 14, 2017Related Files:
- PCB Design FilesZIP 2.7 MB Jul 11, 2017Related Files:
- GuidePDF 273 KB Jul 11, 2017Related Files:
- Application NotePDF 214 KB May 01, 2017AI-generated Summary: Renesas GaN FETs have an absolute maximum gate-to-source voltage rating of ±18V. Transient voltages exceeding this rating may appear at the gate pin due to package inductance but do not damage the device because the internal gate voltage remains within limits. High-frequency ringing on the gate pin results from parasitic inductances in the input and source loops, especially source inductance shared by input and output. Devices with internal ferrite beads, such as TO-247 packages, further attenuate these transients. Careful PCB layout minimizing parasitic inductances is crucial to reduce overshoot, ringing, and improve stability in GaN FET circuits.
- GuidePDF 391 KB Apr 17, 2017
- Application NotePDF 430 KB Jan 13, 2017AI-generated Summary: GaN FETs do not have a body diode or avalanche mechanism like silicon MOSFETs, enabling higher efficiency and new circuit topologies. Instead of avalanche ratings, GaN FETs have a transient peak voltage rating (VTDS) about 25% above their continuous rating, allowing voltage spikes up to 800V for 1µs. Renesas performs high voltage off-state tests to ensure reliability, predicting device lifetimes exceeding 10,000 years under rated conditions. Testing methods avoid unclamped inductive load tests and focus on leakage current measurements to confirm maximum voltage ratings.
- Application NotePDF 1.02 MB Sep 09, 2014AI-generated Summary: GaN power HEMTs enable diode-free bridge circuits by allowing bidirectional current flow without additional freewheeling diodes, reducing conduction losses and reverse recovery charge significantly compared to silicon MOSFETs. The cascode GaN switch improves efficiency by minimizing voltage drop during reverse conduction. PCB layout critically affects performance; minimizing parasitic inductances in output and gate-drive loops reduces overshoot, ringing, and switching losses. Proper placement of transistors, use of low impedance power/ground planes, and strategic bypass capacitor positioning optimize transient current paths and reduce switching node capacitance, enhancing overall stability and efficiency.
Recommended Documents (1)
Datasheets (1)
- GuidePDF 225 KB Jul 14, 2017Related Files:
- GuidePDF 273 KB Jul 11, 2017Related Files:
- GuidePDF 391 KB Apr 17, 2017
Manuals & Guides (3)
- White PaperPDF 1.9 MB R16WP0012EU0100 Rev.1.00 Dec 19, 2025D-Mode GaN combines the best of both GaN and Silicon and is ideal for high-voltage applications with high-speed, high-voltage GaN switching, robust 4V threshold gate compatible with standard gate drivers, and a range of standard package offerings not available with other GaN technologies.
- Application NotePDF 372 KB Dec 11, 2024AI-generated Summary: GaN power switches require careful PCB layout and probing techniques to fully utilize their fast switching capabilities. Minimizing parasitic inductances and capacitances in the power and gate drive loops reduces ringing and ensures stable operation. A large ground plane, close placement of power components, and short, wide traces in the gate drive circuit improve performance. Accurate probing demands short ground leads and direct probe placement to avoid measurement artifacts. Avoid adding parasitics during probing by using floating oscilloscopes and minimizing wire lengths. The document also highlights the importance of proper decoupling and grounding strategies for high-frequency switching circuits.
- Application NotePDF 380 KB Dec 11, 2024AI-generated Summary: Renesas GaN Power Switches combine a normally-off low voltage Si MOSFET and a normally-on high voltage GaN HEMT in a cascode configuration, enabling ultra-fast switching with low reverse recovery charge. This design minimizes switching losses and improves reverse conduction performance compared to traditional silicon MOSFETs. The GaN switch operates in three modes: forward blocking, forward conduction, and reverse conduction, with significantly reduced reverse recovery charge and time, enhancing efficiency in power applications. Reverse recovery tests show the GaN switch has 25 times lower recovery charge than comparable CoolMOS devices, demonstrating superior performance.
- Application NotePDF 214 KB May 01, 2017AI-generated Summary: Renesas GaN FETs have an absolute maximum gate-to-source voltage rating of ±18V. Transient voltages exceeding this rating may appear at the gate pin due to package inductance but do not damage the device because the internal gate voltage remains within limits. High-frequency ringing on the gate pin results from parasitic inductances in the input and source loops, especially source inductance shared by input and output. Devices with internal ferrite beads, such as TO-247 packages, further attenuate these transients. Careful PCB layout minimizing parasitic inductances is crucial to reduce overshoot, ringing, and improve stability in GaN FET circuits.
- Application NotePDF 430 KB Jan 13, 2017AI-generated Summary: GaN FETs do not have a body diode or avalanche mechanism like silicon MOSFETs, enabling higher efficiency and new circuit topologies. Instead of avalanche ratings, GaN FETs have a transient peak voltage rating (VTDS) about 25% above their continuous rating, allowing voltage spikes up to 800V for 1µs. Renesas performs high voltage off-state tests to ensure reliability, predicting device lifetimes exceeding 10,000 years under rated conditions. Testing methods avoid unclamped inductive load tests and focus on leakage current measurements to confirm maximum voltage ratings.View More (6)
Application Notes & White Papers (6)
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