Features
- CPU：Cortex-A7 (500MHz), Cortex-M3(125MHz)
- Voltage: 3V for IO, 1.15V for CPU
- Package: 196 pin LFBGA (12 x12mm, 0.8 pitch), 324 pin LFBGA (15 x15mm, 0.8 pitch)
- Memory: SRAM 6MB with ECC
- Ethernet port: max 5
- Independent GMAC: max 2 (IEEE1588 Compliant)
- Security option: Available
- Ethernet Switch
- EtherCAT slave controller, SERCOSⅢ slave controller
- Others: PLL, RTC
Description
RZ/N1S housed Cortex®-A7 and a large size of built-in RAM in a small package. Since peripheral parts can be reduced, it can be used for small PLC, HMI, etc. In addition, since it has a proven Renesas R-IN engine (“R-IN engine”) as an accelerator for industrial Ethernet communication, it can be used for protocol gateway, sensor hub, etc.
Parameters
| Attributes | Value |
|---|---|
| CPU Architecture | Arm |
| Main CPU | Cortex-A7 |
| Program Memory (KB) | 0 |
| RAM (KB) | 6144 |
| Carrier Type | Bulk (Tray) |
| Supply Voltage (V) | 3 - 3.6 |
| I/O Ports | 95, 160 |
| NPU | No |
| DRAM I/F | DDR2-500/DDR3-1000 |
| 3D GPU | No |
| Temp. Range (°C) | Tj = -40 to +110 |
| Operating Freq (Max) (MHz) | 500 |
| Ethernet speed | 10M/100M/1G |
| Ethernet (ch) | 5 |
| EtherCat (ch) (#) | 1 |
| USB FS (host ch/device ch) | ( 2 / 1 ) |
| USB HS (host ch/device ch) | ( 2 / 1 ) |
| USB SS (host ch/device ch) | ( 0 / 0 ) |
| PCI Express (generation and ch) | No |
| SCI or UART (ch) | 8 |
| SPI (ch) | 6 |
| I2C (#) | 2 |
| CAN (ch) | 2 |
| CAN-FD (ch) | 0 |
| Wireless | No |
| SDHI (ch) | 2 |
| High Resolution Output Timer | No |
| PWM Output (pin#) | 16 |
| 32-Bit Timer (ch) | 4 |
| 16-Bit Timer (ch) (#) | 12 |
| 8-Bit Timer (ch) | 0 |
| Standby operable timer | No |
| Asynchronous General Purpose Timer / Interval Timer (ch) | 0 |
| 16-Bit A/D Converter (ch) | 0 |
| 14-Bit A/D Converter (ch) | 0 |
| 12-Bit A/D Converter (ch) | 8 |
| 10-Bit A/D Converter (ch) | 0 |
| 24-Bit Sigma-Delta A/D Converter (ch) | 0 |
| 16-Bit D/A Converter (ch) | 0 |
| 12-Bit D/A Converter (ch) | 0 |
| 10-Bit D/A Converter (ch) (#) | 0 |
| 8-Bit D/A Converter (ch) | 0 |
| Capacitive Touch Sensing Unit (ch) | 0 |
| Graphics LCD Controller | No, Yes |
| MIPI Interfaces (DSI) (ch) | 0 |
| MIPI Interfaces (CSI) (ch) | 0 |
| Image Codec | No |
| Segment LCD Controller | No |
| Security & Encryption | No, Secure boot, Unique ID |
Application Block Diagrams
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