Features
- Ultra-low phase noise synthesizer: Jitter below 18fs RMS from 12kHz to 20MHz with a 4MHz high pass filter (HPF)
- Independent synchronization domains: Three independent low phase noise synchronization domains
- Frequency domains: Four independent low phase noise frequency domains
- Protocol support: Compatible with JESD204B/C standards
- Time synchronization features: Equipped with a time-to-digital converter (TDC), time of day (TOD) counter, and precision time protocol (PTP) clocks
- Clock outputs: 12 clock outputs with independent integer dividers
- 8 outputs using LVDS, HCSL (AC-LVPECL), or CML
- 4 outputs using LVDS, HCSL (AC-LVPECL), or LVCMOS
- Output frequency range
- CML: DC to 2.5GHz
- LVDS or HCSL: DC to 1GHz
- LVCMOS: DC to 250MHz
- Input clock specifications
- Clock inputs: Four differential or single-ended clock inputs
- Voltage tolerance: Clock inputs tolerate 1.8V input when the device is powered off, sinking less than 1mA
- Input frequency range: CLKIN input frequency from DC to 1GHz
- Time sync TDC: Supports 1 pulse per second (1PPS) and pulse per two seconds (PP2S) inputs
- Digital phase-locked loops (DPLLs)
- Comply with ITU-T G.8262 and G.8262.1 standards
- Input-to-output phase variation ≤ 100ps
- Digitally controlled oscillator (DCO): Frequency resolution < 10^-13
- Operating voltage: Functions on a 1.8V supply
- Packaging: Compact 9mm x 9mm size in a 100-pin BGA
Description
The RC38312 is an ultra-low phase noise radio synchronizer, multi-frequency clock synthesizer, and digitally controlled oscillator (DCO). It delivers exceptional performance for 5G radio units (RU), distribution units (DU), and network switches and routers. Its capability to output clocks with ultra-low in-band phase noise and significantly reduced spurious levels enhances the reliability and efficiency of 4G and 5G RF transceivers. The device offers the most margin on reference clock jitter, with up to three synchronization domains and four frequency domains, allowing designers to simplify their overall PCB design and providing a single timing solution supporting both synchronization via CPRI or eCPRI and RF clock generation. It offers low power dissipation and a smaller area while still achieving ultra-low jitter, and maintains ultra-low phase coherence essential for 5G and 5G-A BTS radio unit designs. The RC38312 provides flexibility by allowing locking to external reference clocks or free-running crystals/oscillators and features hitless reference switching to ensure uninterrupted service even when switching between redundant timing sources, making it an ideal choice for ensuring robust, precise timing across telecommunication applications.
Try the Custom Part Configuration Utility.
Parameters
| Attributes | Value |
|---|---|
| Outputs (#) | 12 |
| Output Type | HCSL, LVCMOS, LVDS |
| Output Freq Range (MHz) | 5.0E-7 - 1000 |
| Input Freq (MHz) | 5.0E-7 - 1000 |
| Inputs (#) | 8 |
| Input Type | CML, Crystal, HCSL, LVCMOS, LVDS, LVPECL |
| Output Banks (#) | 12 |
| Core Voltage (V) | 1.8V, 3.3V |
| Output Voltage (V) | 1.8 |
| Product Category | FemtoClock 3 |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| CABGA | 9.0 x 9.0 x 1.1 | 100 | 0.8 |
Applications
- 5G radio units (RU)
- 5G distribution units (DU), switches, and routers
- Reference clock for 112Gbps and 224Gbps SerDes
- High-performance DCO for precision time protocol (PTP) based clocks
- Datacenter switch, accelerator card, AI interconnect
Try the Custom Part Configuration Utility.
| Part Number | Status | Samples | Stock | Package | Wireless | Output Type | Inputs (#) | Input Type | Output Banks (#) | Pkg. Dimensions (mm) | Carrier Type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| RC38312A100GBB#BC0 | Active | Available | In Stock | CABGA | 1 | HCSL, LVCMOS, LVDS | 8# | CML, Crystal, HCSL, LVCMOS, LVDS, LVPECL | 12# | 9.0 x 9.0 x 1.1 | Tray |
| RC38312A100GBB#HC0 | Active | N/A | Out of Stock | CABGA | 1 | HCSL, LVCMOS, LVDS | 8# | CML, Crystal, HCSL, LVCMOS, LVDS, LVPECL | 12# | 9.0 x 9.0 x 1.1 | Reel |
| RC38312A200GBB#BC0 | Active | Available | In Stock | CABGA | 1 | HCSL, LVCMOS, LVDS | 8# | CML, Crystal, HCSL, LVCMOS, LVDS, LVPECL | 12# | 9.0 x 9.0 x 1.1 | Tray |
| RC38312A200GBB#HC0 | Active | Available | Out of Stock | CABGA | 1 | HCSL, LVCMOS, LVDS | 8# | CML, Crystal, HCSL, LVCMOS, LVDS, LVPECL | 12# | 9.0 x 9.0 x 1.1 | Reel |
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- Product AdvisoryPDF 114 KB Jun 08, 2026
- Application NotePDF 1.13 MB R31AN0075EU0105 Rev.1.05 May 22, 2026AI-generated Summary: The document explains how to program external I2C serial EEPROMs for FemtoClock3 (FC3) and FemtoClock3 Wireless (FC3W) devices, detailing hardware connections, EEPROM addressing, and configuration loading processes. It covers the EEPROM payload sizes (4kB for FC3 and 2kB for FC3W), I2C speeds supported (100kHz, 400kHz, 1MHz), and the timing calculation for EEPROM startup and calibration. The hardware setup sections describe evaluation board schematics, EEPROM pin configurations, address selection via jumpers, and write-protect control. It also discusses managing I2C bus mastership during EEPROM loading and provides guidance on using GUI tools and recommended EEPROM vendors.
- Application NotePDF 576 KB R31AN0066EU0114 Rev.1.14 May 22, 2026
- Application NotePDF 1.53 MB R31AN0034EU0102 Rev.1.02 Oct 21, 2025AI-generated Summary: PLL loop filter design involves selecting component values to ensure stable operation and optimized phase noise. The loop bandwidth depends on parameters like charge pump current, VCO gain, and feedback divider. Second and third order passive loop filters are common, with specific calculations for cutoff, zero, and pole frequencies guiding component selection. Proper tuning of loop bandwidth enhances PLL stability and phase noise performance, demonstrated through lab experiments and calculation examples.
- GuidePDF 2.64 MB R31DS0028EU0103 Rev.1.03 Aug 20, 2025
- Application NotePDF 3.84 MB R31AN0092EU0100 Rev.1.00 Aug 01, 2025
- Application NotePDF 991 KB R31AN0091EU0100 Rev.1.00 May 07, 2025
- Manual - SoftwarePDF 2.87 MB R31US0030EU0102 Rev.1.02 May 07, 2025
- Application NotePDF 488 KB R31AN0088EU0100 Rev.1.00 Apr 14, 2025AI-generated Summary: Open Radio Units (O-RUs) require precise time synchronization achieved through a well-designed clock tree using protocols like Precision Time Protocol (PTP), Synchronous Ethernet (SyncE), and Global Navigation Satellite Systems (GNSS). Phase-Locked Loops (PLLs) play a vital role by filtering jitter, enabling frequency synthesis, and maintaining holdover stability. The AMD ZCU670 platform enhances synchronization with hardware timestamping and high-performance PLLs. FemtoClock 3 Wireless provides frequency synthesis, jitter filtering, phase alignment, and dynamic reconfiguration, delivering ultra-precise timing with low power consumption and compact integration. Linux-based drivers support integration with open-source PTP software for robust O-RU synchronization in Open-RAN networks.
- Product Change NoticePDF 671 KB Mar 17, 2025
- Application NotePDF 1.04 MB R31AN0063EU0104 Rev.1.04 Jan 09, 2025AI-generated Summary: The document explains how to achieve the stringent jitter and phase noise requirements for 112G PAM-4 SerDes reference clocks using FemtoClock 3 and FemtoClock 3 Wireless devices. It details the ultra-low jitter performance (<60fs RMS) and phase noise margins that exceed standard requirements. It covers clock generation, jitter cleaning, synchronization features, and the use of specific crystal frequencies and measurement methods to meet 112G standards. The document also discusses applying 4MHz high-pass filters in phase noise measurements and provides crystal recommendations for optimal performance.
Recommended Documents (1)
Datasheets (5)
- GuidePDF 2.64 MB R31DS0028EU0103 Rev.1.03 Aug 20, 2025
- Manual - SoftwarePDF 2.87 MB R31US0030EU0102 Rev.1.02 May 07, 2025
- Manual - SoftwarePDF 2.21 MB R31US0012EU0102 Rev.1.02 May 23, 2024
- Manual - SoftwarePDF 1.94 MB R31US0027EU0101 Rev.1.01 Jul 06, 2023
Manuals & Guides (4)
- Application NotePDF 1.13 MB R31AN0075EU0105 Rev.1.05 May 22, 2026AI-generated Summary: The document explains how to program external I2C serial EEPROMs for FemtoClock3 (FC3) and FemtoClock3 Wireless (FC3W) devices, detailing hardware connections, EEPROM addressing, and configuration loading processes. It covers the EEPROM payload sizes (4kB for FC3 and 2kB for FC3W), I2C speeds supported (100kHz, 400kHz, 1MHz), and the timing calculation for EEPROM startup and calibration. The hardware setup sections describe evaluation board schematics, EEPROM pin configurations, address selection via jumpers, and write-protect control. It also discusses managing I2C bus mastership during EEPROM loading and provides guidance on using GUI tools and recommended EEPROM vendors.
- Application NotePDF 576 KB R31AN0066EU0114 Rev.1.14 May 22, 2026
- Application NotePDF 1.53 MB R31AN0034EU0102 Rev.1.02 Oct 21, 2025AI-generated Summary: PLL loop filter design involves selecting component values to ensure stable operation and optimized phase noise. The loop bandwidth depends on parameters like charge pump current, VCO gain, and feedback divider. Second and third order passive loop filters are common, with specific calculations for cutoff, zero, and pole frequencies guiding component selection. Proper tuning of loop bandwidth enhances PLL stability and phase noise performance, demonstrated through lab experiments and calculation examples.
- Application NotePDF 3.84 MB R31AN0092EU0100 Rev.1.00 Aug 01, 2025View More (33)
Application Notes & White Papers (33)
- Product AdvisoryPDF 114 KB Jun 08, 2026
- Product Change NoticePDF 671 KB Mar 17, 2025
Product Notices (PCN, EOL, etc) (2)
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- PCB Design FilesZIP 7.18 MB RC38312_FC3W_EVB_Design_Files Rev.0.00 Oct 16, 2024
- SchematicPDF 267 KB RC38312 FC3W BGA100 Reference design Schematic-Dec-15-2023 Rev.0.00 Dec 15, 2023
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- ReportPDF 14.43 MB R31UZ0008EU0100 Rev.1.00 Oct 04, 2024
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Renesas Boards & Kits
FemtoClock 3 Wireless Ultra-Low Phase Noise Synchronizer and Jitter Attenuator Evaluation Kit
This RC38312A evaluation kit is used to evaluate the RC38312 FemtoClock™ 3 ultra-low phase noise radio synchronizer, multi-frequency clock synthesizer. The RC38312/RC38112 is an ultra-low phase noise radio synchronizer, multi-frequency clock synthesizer, and digitally controlled oscillator... Read More
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- Software PackageThe Renesas IC Toolbox (RICBox) software platform enables customers to configure Renesas devices on evaluation kits when attached to the computer running the software.
- Software & Tools - SoftwareZIP 383 KB femtoclock3-api_1-0-3_435713_37a49585 Dec 17, 2024
- PCB Design FilesZIP 7.18 MB RC38312_FC3W_EVB_Design_Files Rev.0.00 Oct 16, 2024
- SchematicPDF 267 KB RC38312 FC3W BGA100 Reference design Schematic-Dec-15-2023 Rev.0.00 Dec 15, 2023
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- Software & Tools - SoftwareZIP 383 KB femtoclock3-api_1-0-3_435713_37a49585 Dec 17, 2024
- PCB Design FilesZIP 7.18 MB RC38312_FC3W_EVB_Design_Files Rev.0.00 Oct 16, 2024
- SchematicPDF 267 KB RC38312 FC3W BGA100 Reference design Schematic-Dec-15-2023 Rev.0.00 Dec 15, 2023
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FemtoClock™ 3 Wireless is an industry-leading, ultra-low phase noise synchronizer and jitter attenuator for 5G distribution units (DU), switches, and routers. RC38312 and RC38112 are designed for 5G and 5G-A BTS radio unit designs.
Learn about the FemtoClock 3 Wireless ultra-low phase noise synchronizer and jitter attenuator for 5G radio units, distribution units, and high-performance precision timing protocol.
News & Blog Posts
Blog Post
Oct 8, 2024
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Knowledge Base
-
Do you have a reference design for the RC38312?
Yes, we have a reference design based on the BGA100 device. See attached schematic.
Oct 8, 2024 -
How can I achieve the best performance for the FemtoClock 3 Wireless in regards to phase noise with the lowest crosstalk.
FemtoClock 3 (FC3) and FemtoClock 3 Wireless (FC3W) devices are a family of telecom integrated circuits that are low-phase noise jitter attenuators. These include the RC32312 and RC32308 (FC3) or the RC38108, RC38208, RC38112 and RC38312 (FC3W). There are also FC3 devices that are only frequency clock synthesizers, such ...
Oct 8, 2024