Features
- Maximum Ratings Supply voltage Vcc: 24 V Junction temperature Tj: from –40 to +150 degrees centigrade
- Electrical characteristics VFB feedback voltage VREF: 2.5 V ± 1.5% UVLO (Undervoltage Lockout) operation start voltage VH: 10.4 V ± 0.7 V UVLO operation shutdown voltage VL: 8.9 V ± 0.5 V UVLO hysteresis voltage Hysuvl : 1.5 V ± 0.5 V
- Functions Boost converter control with continuous conduction mode Interleaving control Frequency modulation (*2) Brownout Phase drop (*1) External clock synchronization input External clock synchronization output (*1) Two modes of over voltage protections Mode 1: Dynamic OVP preventing over voltage after sudden variation of load. Mode 2: Static OVP preventing over voltage in the period of normal operation. Feedback loop wire breaking/open detector Dual over voltage protection circuits (*1): FB and OVP2 terminals Current balance control Phase 1 and Phase 2 independent over current protection Package line-up Pb-free LQFP-40 (R2A20114AFP) Pb-free SOP-20 (R2A20114ASP) Notes: *1 Supported only by R2A20114AFP *2 Frequency modulation periods (dfm) of R2A20114ASP are fixed.
Description
Support is limited to customers who have already adopted these products.
R2A20114AFP/ASP is a boost converter control IC with PFC (Power Factor Correction). Employing continuous conduction mode interleaving PFC, it performs higher efficiency and lower switching noise even for high power use. Interleaving control of the boost converters, namely, producing 180 degrees phase shift between the output signals (GD1, 2) driving the boost converters, enables the system to perform high conversion efficiency and low switching noises and, at the same time, to reduces ripple currents in input and output current and then this allows use of smaller components such as boost inductors, input filters and output capacitors. R2A20114AFP/ASP integrates a various kinds of protection circuits, such as the detection circuit of breaking of wire in feedback loop, two modes of over voltage protection circuits, over current protection circuit and error output circuit (*1 ), which improve the reliability of the power supply system and reduce the number of component parts on the system.
| Part Number | Status | Samples | Stock | RoHS | Package | Budgetary Price (USD) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|
| R2A20114AFP#W1 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LQFP | |||
| R2A20114AFP#W5 | Obsolete | N/A | Out of Stock | Contact | LQFP | 1ku | $5.45 | MALAYSIA | JAPAN |
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- Product Change Notice
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- Application NotePDF 1.02 MB R03AN0007EJ0300 Rev.3.00 May 15, 2014AI-generated Summary: The document explains the functional blocks of the R2A20114A, focusing on protection features such as over voltage protection (OVP), over voltage protection 2 (OVP2), feedback open loop detection, and over current protection (OCP). OVP uses dynamic and static stages to control MOSFET operation and prevent noise. OVP2 monitors PFC output voltage to stop switching when necessary. Feedback open loop detection disables the GD signal if feedback voltage is too low. OCP disables GD signals when current exceeds a threshold. The drive stage supports two totem-pole outputs with specific peak drivability, and soft start gradually increases ON time via a capacitor on the SS pin, with adjustable timing and discharge conditions.
- Application NotePDF 1.3 MB R19AN0015ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for a dual port Ethernet PHY device supporting 10Base-T, 100Base-TX, and 100Base-FX. It covers strap pin configuration options for initial start-up settings, detailing the use of pull-up and pull-down resistors, including recommended resistor values and schematic examples. The strap pins function only during power-up or reset, with internal and external resistor configurations advised for noise immunity. Additional chapters address media interfaces, power supply layout, clock input, LED control, and unused pins.
- Application NotePDF 1.21 MB R19AN0014ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for Dual PHY and Single Channel PHY ASSP devices. It covers strap pin configuration options for initial start-up settings, including pull-up and pull-down resistor values and configurations to ensure stable operation in noisy environments. The layout guidelines include power supply design, differential pair routing, media-dependent interfaces, MAC interfaces, and clock input circuits. Examples and tables illustrate resistor values and schematic configurations for strap pins.
- Application NotePDF 224 KB R03AN0009EJ0100 Rev.1.00 Feb 22, 2012AI-generated Summary: The document explains the internal functions of the R2A20112A IC, focusing on its UVLO block which prevents operation under low voltage, and the 5 V reference voltage used internally. It details the Error Amplifier that stabilizes PFC output voltage, the Zero Current Detection circuit essential for CRM operation, and the RAMP generator that controls PWM ON time using external components. The drive stage outputs pulses to power MOSFETs with specific peak current capabilities and includes driver circuit examples for different MOSFET gate charges.
- Application NoteAI-generated Summary: The built-in oscillator frequency depends on an external resistor and a 10 pF capacitor, with a maximum 50% duty cycle at 48 kHz. The oscillator charges and discharges the capacitor between 0.2 V and 2 V. The error amplifier uses a transconductance amplifier to regulate output based on feedback voltage. The output pin drives an external MOSFET with up to 900 mA peak current. The peak current control circuit maintains constant inductor current using overcurrent protection via the CS pin. The constant ON time control uses feedback from the FB pin to regulate inductor current, adjusting peak current proportionally to input voltage for power factor correction.
- Application NotePDF 397 KB an1684 Jan 19, 2004AI-generated Summary: The document outlines important legal disclaimers and usage guidelines for semiconductor products. It emphasizes user responsibility for product design and safety, disclaims liability for damages, and clarifies no intellectual property licenses are granted. Products are categorized by quality grades with specific application recommendations. Users must comply with laws, avoid unauthorized modifications, and ensure safe use within specified conditions. Contact details for Renesas Electronics sales offices worldwide are provided.
- Application NotePDF 509 KB an1681 Jan 19, 2004AI-generated Summary: The document explains grounding techniques for PCB layouts using a dual op amp example on a single-layer copper board. It compares three grounding schemes: a center spine ground trace, an outer ground plane, and a split/star ground plane, highlighting the benefits of single-point grounding to minimize noise and antenna effects. It emphasizes following current paths, minimizing loop lengths, and ensuring close forward and return paths to reduce interference. The document also includes disclaimers on product use, quality grades, safety, and legal compliance.
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- Application NotePDF 1.02 MB R03AN0007EJ0300 Rev.3.00 May 15, 2014AI-generated Summary: The document explains the functional blocks of the R2A20114A, focusing on protection features such as over voltage protection (OVP), over voltage protection 2 (OVP2), feedback open loop detection, and over current protection (OCP). OVP uses dynamic and static stages to control MOSFET operation and prevent noise. OVP2 monitors PFC output voltage to stop switching when necessary. Feedback open loop detection disables the GD signal if feedback voltage is too low. OCP disables GD signals when current exceeds a threshold. The drive stage supports two totem-pole outputs with specific peak drivability, and soft start gradually increases ON time via a capacitor on the SS pin, with adjustable timing and discharge conditions.
- Application NotePDF 1.3 MB R19AN0015ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for a dual port Ethernet PHY device supporting 10Base-T, 100Base-TX, and 100Base-FX. It covers strap pin configuration options for initial start-up settings, detailing the use of pull-up and pull-down resistors, including recommended resistor values and schematic examples. The strap pins function only during power-up or reset, with internal and external resistor configurations advised for noise immunity. Additional chapters address media interfaces, power supply layout, clock input, LED control, and unused pins.
- Application NotePDF 1.21 MB R19AN0014ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for Dual PHY and Single Channel PHY ASSP devices. It covers strap pin configuration options for initial start-up settings, including pull-up and pull-down resistor values and configurations to ensure stable operation in noisy environments. The layout guidelines include power supply design, differential pair routing, media-dependent interfaces, MAC interfaces, and clock input circuits. Examples and tables illustrate resistor values and schematic configurations for strap pins.
- Application NotePDF 224 KB R03AN0009EJ0100 Rev.1.00 Feb 22, 2012AI-generated Summary: The document explains the internal functions of the R2A20112A IC, focusing on its UVLO block which prevents operation under low voltage, and the 5 V reference voltage used internally. It details the Error Amplifier that stabilizes PFC output voltage, the Zero Current Detection circuit essential for CRM operation, and the RAMP generator that controls PWM ON time using external components. The drive stage outputs pulses to power MOSFETs with specific peak current capabilities and includes driver circuit examples for different MOSFET gate charges.
- Application NoteAI-generated Summary: The built-in oscillator frequency depends on an external resistor and a 10 pF capacitor, with a maximum 50% duty cycle at 48 kHz. The oscillator charges and discharges the capacitor between 0.2 V and 2 V. The error amplifier uses a transconductance amplifier to regulate output based on feedback voltage. The output pin drives an external MOSFET with up to 900 mA peak current. The peak current control circuit maintains constant inductor current using overcurrent protection via the CS pin. The constant ON time control uses feedback from the FB pin to regulate inductor current, adjusting peak current proportionally to input voltage for power factor correction.View More (7)
Application Notes & White Papers (7)
- Product Change Notice
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Product Notices (PCN, EOL, etc) (3)
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Errata & Technical Updates (2)
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