Features
- 4.5V to 5.25V input voltage range
- 7 programmable step-down converters - 5 with integrated FETs
- Supports P9147 and P9148 distributed power units (DPU)
- Seven general-purpose LDOs including Source Sink VTT
- SVID interface supporting IMVP7 protocol
- 10-bit ADC
- 16 programmable GPIOs and 12 programmable Enable outputs
- Host interface and system power management functions
- High-speed I2C interface
- Factory programmable default power sequence and settings
- Industrial temperature range of -40 °C to +85 °C
- 100-lead 8mm x 8mm dual-row QFN (Type4-PCB) HD package option (NQG100)
- 100-lead 9mm x 9mm dual-row HLA (Type3-PCB) LD package option (NAG100)
IDTP9145-IDTP9147 Application Diagram
Description
The P9145 is a programmable, multi-channel power management IC (PMIC) designed for the Intel® Baytrail Atom™ SoC to meet high-performance requirements and provide high-feature integration to minimize system board area and BOM cost. The PMIC includes subsystems for voltage regulation, power sequencing management, A/D conversion, GPIOs, PWMs, and others. The P9145 is factory-programmable for application-specific sequencing and output voltage requirements. The device supports the serial voltage ID (SVID) interface for VCC, VNN, and VDDQ (optional). The output current capability of the P9145 solution can be increased by adding Renesas intelligent, scalable, distributed power units (DPU), P9147 and P9148.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Carrier (#) | Package Area (mm²) | Pkg. Dimensions (mm) | Qty. per Reel (#) | Tape & Reel | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| P9145-I0NAGI | Obsolete | N/A | Out of Stock | HLA | 100# | Tray | 3 | 207# | 81mm² | 9.0 x 9.0 x 0.9 | 0 | No | Yes | e3 Sn | -40 to 85°C |
| P9145-I0NAGI8 | Obsolete | N/A | Out of Stock | HLA | 100# | Reel | 3 | 0 | 81mm² | 9.0 x 9.0 x 0.9 | 3000# | Yes | Yes | e3 Sn | -40 to 85°C |
| P9145-I0NQGI | Obsolete | N/A | Out of Stock | VFQFPN | 100# | Tray | 3 | 260# | 64mm² | 8.0 x 8.0 x 0.77 | 0 | No | Yes | e3 Sn | -40 to 85°C |
| P9145-I0NQGI8 | Obsolete | N/A | Out of Stock | VFQFPN | 100# | Reel | 3 | 0 | 64mm² | 8.0 x 8.0 x 0.77 | 3000# | Yes | Yes | e3 Sn | -40 to 85°C |
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- Application NoteAI-generated Summary: Guidelines focus on optimal component selection, placement, and routing for IDTP9145 PMIC and IDTP9147/9148 DPUs to maximize performance. Minimizing parasitic inductance in PVIN power supply traces is critical, recommending parallel input capacitors to reduce ESL and output capacitors with proper voltage ratings to ensure regulator stability. The PVIN capacitor placement near inner-row PVIN pins requires short traces and multiple parallel vias to reduce parasitic effects. The IDTP9145 offers QFN and HLA packages, with HLA supporting 4-layer PCBs and easier via placement. Proper via arrays connect the exposed pad (power ground) to ground planes, ensuring effective current return. PCB layout examples emphasize minimizing ground plane perforation and careful via usage to maintain current flow and thermal performance.
- Overview
- DatasheetIDTP9145 Advanced DatasheetRECOMMENDED
- Product Change NoticePDF 881 KB 7WDXRDKU4E7E-5-59928 Feb 15, 2016
- DatasheetIDTP9145 Advanced DatasheetRECOMMENDED
Recommended Documents (1)
- DatasheetIDTP9145 Advanced DatasheetRECOMMENDED
Datasheets (1)
Manuals & Guides (1)
- Application NoteAI-generated Summary: Guidelines focus on optimal component selection, placement, and routing for IDTP9145 PMIC and IDTP9147/9148 DPUs to maximize performance. Minimizing parasitic inductance in PVIN power supply traces is critical, recommending parallel input capacitors to reduce ESL and output capacitors with proper voltage ratings to ensure regulator stability. The PVIN capacitor placement near inner-row PVIN pins requires short traces and multiple parallel vias to reduce parasitic effects. The IDTP9145 offers QFN and HLA packages, with HLA supporting 4-layer PCBs and easier via placement. Proper via arrays connect the exposed pad (power ground) to ground planes, ensuring effective current return. PCB layout examples emphasize minimizing ground plane perforation and careful via usage to maintain current flow and thermal performance.
Application Notes & White Papers (1)
- Product Change NoticePDF 881 KB 7WDXRDKU4E7E-5-59928 Feb 15, 2016
Product Notices (PCN, EOL, etc) (2)
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