Features
- 5.6V to 12.6V input voltage range
- Output voltage controlled by host PMIC (P9145)
- Up to 6A peak output current per device/phase
- 2.0MHz switching frequency, internal PWM generation
- Support automatic phase-shedding, PFM and LDO modes
- Simple 2-wire interface for device configuration, control, and status exchange to the host PMIC
- Automatic detection by Host PMIC
- No analog feedback to PMIC required
- Digital modulation and ML-based error correction
- Industrial temperature range of -40 °C to +85 °C
- 12-lead 3mm x 4mm DFN
Description
Flexible output current capabilities are key to address modern multi-core SoC solutions with a variety of different skews. The P9147 distributed power units (DPU) operate as additional phases to the P9145 PMIC to increase the output current of the solution. The device works as a controlled current source fully controlled by the host PMIC. Multiple P9147 devices may be used in parallel to provide additional current to the load. A high-speed proprietary interface between the P9145 and the P9147 provides control and feedback information. The device seamlessly integrates into the PMIC ecosystem and is flexible and transparent to the user. The P9147 has been designed for systems with high voltage supplies, like 12V ATX-based or multi-cell battery stack systems.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|
| P9147NRGI8 | Obsolete | N/A | Out of Stock | DFN | 12# | Reel | 1 | Yes | e3 Sn | -40 to 85°C |
Filters
Applied Filters
- Application NoteAI-generated Summary: Guidelines focus on optimal component selection, placement, and routing for IDTP9145 PMIC and IDTP9147/9148 DPUs to maximize performance. Minimizing parasitic inductance in PVIN power supply traces is critical, recommending parallel input capacitors to reduce ESL and output capacitors with proper voltage ratings to ensure regulator stability. The PVIN capacitor placement near inner-row PVIN pins requires short traces and multiple parallel vias to reduce parasitic effects. The IDTP9145 offers QFN and HLA packages, with HLA supporting 4-layer PCBs and easier via placement. Proper via arrays connect the exposed pad (power ground) to ground planes, ensuring effective current return. PCB layout examples emphasize minimizing ground plane perforation and careful via usage to maintain current flow and thermal performance.
- DatasheetIDTP9147 Advanced DatasheetRECOMMENDED
- DatasheetIDTP9147 Advanced DatasheetRECOMMENDED
Recommended Documents (1)
- DatasheetIDTP9147 Advanced DatasheetRECOMMENDED
Datasheets (1)
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- Application NoteAI-generated Summary: Guidelines focus on optimal component selection, placement, and routing for IDTP9145 PMIC and IDTP9147/9148 DPUs to maximize performance. Minimizing parasitic inductance in PVIN power supply traces is critical, recommending parallel input capacitors to reduce ESL and output capacitors with proper voltage ratings to ensure regulator stability. The PVIN capacitor placement near inner-row PVIN pins requires short traces and multiple parallel vias to reduce parasitic effects. The IDTP9145 offers QFN and HLA packages, with HLA supporting 4-layer PCBs and easier via placement. Proper via arrays connect the exposed pad (power ground) to ground planes, ensuring effective current return. PCB layout examples emphasize minimizing ground plane perforation and careful via usage to maintain current flow and thermal performance.
Application Notes & White Papers (1)
Product Notices (PCN, EOL, etc) (1)
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