Features
- 1.5GHz analog input bandwidth
- 60fs clock jitter
- Programmable gain, offset and skew control
- Over-range indicator
- Selectable clock divider: ÷1, ÷2 or ÷4
- Clock phase selection
- Nap and sleep modes
- Two's complement, gray code or binary data format
- DDR LVDS-compatible or LVCMOS outputs
- Programmable built-in test patterns
- Single-supply 1.8V operation
- Pb-free (RoHS compliant)
Description
The KAD5510P is a family of low power, high performance 10-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The KAD5510P is part of a pin-compatible portfolio of 10-, 12- and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS. A Serial Peripheral Interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset. Digital output data is presented in selectable LVDS or CMOS formats. The KAD5510P is available in a 48 Ld QFN package with an exposed paddle. Operating from a 1. 8V supply, performance is specified across the industrial operating temperature range (-40°C to +85°C). Key Specifications $ SNR = 60. 7dBFS for fIN = 105MHz (-1dBFS) $ SFDR = 86. 1dBc for fIN = 105MHz (-1dBFS) $ Total Power Consumption $$ 234/189mW at 250/125MSPS (DDR Mode)
Applications
- Power Amplifier Linearization
- Radar and Satellite Antenna Array Processing
- Broadband Communications
- High-Performance Data Acquisition
- Communications Test Equipment
- WiMAX and Microwave Receivers
| Part Number | Status | Samples | Stock | RoHS | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| KAD5510P-17Q48 | Obsolete | N/A | Out of Stock | RoHS:EN | QFN | 48# | Tray | 3 | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | -40 to +85°C |
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- PCB Design FilesPDF 1.21 MB kdc5512-q48_12h-q48_14-q48 Jul 20, 2018
- Product Change NoticePDF 388 KB PCN16016 Feb 08, 2016
- Application NotePDF 433 KB an1715 Jun 16, 2011AI-generated Summary: The document evaluates the performance of lower resolution ADCs using the KAD5512P-50 device in both 12-bit and 10-bit output modes, presenting detailed signal metrics such as SNR, SFDR, THD, and ENOB at a 500 MHz sampling rate. It includes power consumption data and frequency response graphs. The document also outlines Renesas Electronics' disclaimers on product use, quality grades, safety responsibilities, legal compliance, and contact information for global sales offices.
- Application NotePDF 503 KB an9675 Aug 13, 1999AI-generated Summary: Effective Number of Bits (ENOB) depends critically on precise coherence in A/D sampling, with small frequency shifts significantly impacting accuracy. Unwrapping reconstructs coherently sampled sine waves, while windowing controls spectral leakage by shaping the acquisition window. Resampling and interpolation adjust sample sets to avoid leakage in FFT analysis. Different window functions balance side lobe levels and bandwidth, affecting spectral resolution and leakage reduction.
- Application NotePDF 1.08 MB an002 Nov 19, 1998AI-generated Summary: Data acquisition and conversion involve quantization, where the smallest resolvable analog difference (quantum) depends on the full scale range and resolution. Quantization introduces an irreducible error called quantizing error or noise. Aperture time, the conversion time uncertainty, causes amplitude errors when signals change during conversion. Sample-hold circuits reduce aperture time by storing sampled signals. The Sampling Theorem states that sampling frequency must be at least twice the highest signal frequency to avoid distortion from frequency folding or aliasing. Natural binary code is commonly used for digital representation in converters, with the most and least significant bits defining the code's resolution and value.
- Application NotePDF 287 KB an9705 Feb 21, 1997AI-generated Summary: Coherent sampling requires the ratio of signal frequency to sampling frequency to be a rational number, expressed as ko/N. When this condition is not met, frequency smearing occurs across bins. Data Acquisition Systems (DAS) can mitigate this by windowing, fixing sampling frequency and tuning input frequency, or fixing input frequency and tuning sampling frequency. The latter two methods are practical for most systems. Pseudo-code illustrates the frequency response for non-integer ko values.
- GuidePDF 1.02 MB an1434 May 22, 2008
Recommended Documents (1)
Datasheets (1)
- GuidePDF 1.02 MB an1434 May 22, 2008
Manuals & Guides (2)
- Application NotePDF 433 KB an1715 Jun 16, 2011AI-generated Summary: The document evaluates the performance of lower resolution ADCs using the KAD5512P-50 device in both 12-bit and 10-bit output modes, presenting detailed signal metrics such as SNR, SFDR, THD, and ENOB at a 500 MHz sampling rate. It includes power consumption data and frequency response graphs. The document also outlines Renesas Electronics' disclaimers on product use, quality grades, safety responsibilities, legal compliance, and contact information for global sales offices.
- Application NotePDF 503 KB an9675 Aug 13, 1999AI-generated Summary: Effective Number of Bits (ENOB) depends critically on precise coherence in A/D sampling, with small frequency shifts significantly impacting accuracy. Unwrapping reconstructs coherently sampled sine waves, while windowing controls spectral leakage by shaping the acquisition window. Resampling and interpolation adjust sample sets to avoid leakage in FFT analysis. Different window functions balance side lobe levels and bandwidth, affecting spectral resolution and leakage reduction.
- Application NotePDF 1.08 MB an002 Nov 19, 1998AI-generated Summary: Data acquisition and conversion involve quantization, where the smallest resolvable analog difference (quantum) depends on the full scale range and resolution. Quantization introduces an irreducible error called quantizing error or noise. Aperture time, the conversion time uncertainty, causes amplitude errors when signals change during conversion. Sample-hold circuits reduce aperture time by storing sampled signals. The Sampling Theorem states that sampling frequency must be at least twice the highest signal frequency to avoid distortion from frequency folding or aliasing. Natural binary code is commonly used for digital representation in converters, with the most and least significant bits defining the code's resolution and value.
- Application NotePDF 287 KB an9705 Feb 21, 1997AI-generated Summary: Coherent sampling requires the ratio of signal frequency to sampling frequency to be a rational number, expressed as ko/N. When this condition is not met, frequency smearing occurs across bins. Data Acquisition Systems (DAS) can mitigate this by windowing, fixing sampling frequency and tuning input frequency, or fixing input frequency and tuning sampling frequency. The latter two methods are practical for most systems. Pseudo-code illustrates the frequency response for non-integer ko values.
Application Notes & White Papers (4)
- Product Change NoticePDF 388 KB PCN16016 Feb 08, 2016
Product Notices (PCN, EOL, etc) (1)
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