Features
- Up to 95MSPS input
- Four independently programmable downconverter channels in a single package
- Four parallel 17-bit inputs providing 16-bit fixed or one of several 17-bit floating point formats
- 32-bit programmable carrier NCO with >115dB SFDR
- 110dB FIR out of band attenuation
- Decimation from 4 to >65536
- 24-bit internal data path
- Digital AGC with up to 96dB of gain range
- Filter functions
- 1- to 5-stage CIC filter
- Halfband decimation and interpolation FIR filtering
- Programmable FIR filtering
- Resampling FIR filtering
- Cascadable filtering for additional bandwidth
- Four independent serial outputs
- 2.5V core, 3.3V I/O operation
- Pb-free plus anneal available (RoHS compliant)
Description
The ISL5216 Quad Programmable Digital Downconverter (QPDC) is designed for high dynamic range applications such as cellular basestations where multiple channel processing is required in a small physical space. The QPDC combines into a single package a set of four channels which include: digital mixers, a quadrature carrier NCO, digital filters, a resampling filter, a cartesian to polar coordinate converter, and an automatic gain control (AGC) loop. The ISL5216 accepts four channels of 16-bit fixed or up to 14-bit mantissa/3-bit exponent floating point real or complex digitized IF samples which are mixed with local quadrature sinusoids. Each channel carrier NCO frequency is set independently by the microprocessor. The output of the mixers is filtered with CIC and FIR filters, with a variety of decimation options. Gain adjustment is provided on the filtered signal. The digital AGC provides a gain adjust range of up to 96dB with programmable thresholds and slew rates. A cartesian to polar coordinate converter provides magnitude and phase outputs. A frequency discriminator is also provided to allow FM demodulation. Selectable outputs include I samples, Q samples, magnitude, phase, frequency, and AGC gain. The output resolution is selectable from a 4-bit fixed point to a 32-bit floating point. Output bandwidths in excess of 1MHz are achievable using a single channel. Wider bandwidths are available by cascading or polyphasing multiple channels.
Applications
- Narrow-band TDMA through IS-95 CDMA digital software radio and basestation receivers
- Wide-band applications: W-CDMA and UMTS digital software radio and basestation receivers
| Part Number | Status | Samples | Stock | Package | Carrier Type | MOQ |
|---|---|---|---|---|---|---|
| ISL5216KI | Obsolete | N/A | Out of Stock | FBGA | Tray | 189 |
| ISL5216KI-1 | Obsolete | N/A | In Stock | FBGA | Tray | 126 |
| ISL5216KI-1Z | Obsolete | N/A | In Stock | FBGA | Tray | 126 |
| ISL5216KIZ | Obsolete | N/A | Out of Stock | FBGA | Tray | 189 |
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- Application NotePDF 427 KB an9928 Mar 30, 2001AI-generated Summary: The HSP50216 QPDC implements a 1.2288MSPS receiver for CDMA applications using two of its four channels, enabling up to two receivers per device. It uses a 5th order CIC decimator and polyphase FIR filters to achieve a decimation of 25X, providing 24-bit I and Q data outputs. The design achieves blocker rejection greater than 65dB between 750kHz and 900kHz and over 103dB beyond 900kHz. The filter configuration and frequency responses are detailed, along with clock cycle usage analysis showing room for additional filter taps.
- Application NotePDF 360 KB an9927 Mar 30, 2001AI-generated Summary: The document details the implementation of a UMTS receiver using the ISL5216 with a 76.8MSPS input rate, utilizing two of four channels with CIC and 28-tap FIR filters for decimation and tuning. It explains the filter configurations, clock usage, and output multiplexing methods. The HSP50216 evaluation software supports configuration, register programming, and real-time output display, compatible mainly with Windows 95/98. The software can generate register files independently of hardware connection.
- Application NotePDF 541 KB an9987 Oct 20, 1999AI-generated Summary: The document details the IEEE Standard Test Access Port (TAP) and Boundary Scan Register configuration for the ISL5216. It explains the structure and operation of the 132-bit boundary scan register, including its shift register and parallel output register components. The boundary scan cells for input, output, and three-state pins enable observation and control of circuit pins during testing. The document outlines the behavior of the register in various TAP states and instructions, emphasizing the timing and control of system pins like CLK and WR. It also provides a detailed I/O correspondence table for the boundary scan register pins.
Recommended Documents (1)
Datasheets (1)
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- Application NotePDF 427 KB an9928 Mar 30, 2001AI-generated Summary: The HSP50216 QPDC implements a 1.2288MSPS receiver for CDMA applications using two of its four channels, enabling up to two receivers per device. It uses a 5th order CIC decimator and polyphase FIR filters to achieve a decimation of 25X, providing 24-bit I and Q data outputs. The design achieves blocker rejection greater than 65dB between 750kHz and 900kHz and over 103dB beyond 900kHz. The filter configuration and frequency responses are detailed, along with clock cycle usage analysis showing room for additional filter taps.
- Application NotePDF 360 KB an9927 Mar 30, 2001AI-generated Summary: The document details the implementation of a UMTS receiver using the ISL5216 with a 76.8MSPS input rate, utilizing two of four channels with CIC and 28-tap FIR filters for decimation and tuning. It explains the filter configurations, clock usage, and output multiplexing methods. The HSP50216 evaluation software supports configuration, register programming, and real-time output display, compatible mainly with Windows 95/98. The software can generate register files independently of hardware connection.
- Application NotePDF 541 KB an9987 Oct 20, 1999AI-generated Summary: The document details the IEEE Standard Test Access Port (TAP) and Boundary Scan Register configuration for the ISL5216. It explains the structure and operation of the 132-bit boundary scan register, including its shift register and parallel output register components. The boundary scan cells for input, output, and three-state pins enable observation and control of circuit pins during testing. The document outlines the behavior of the register in various TAP states and instructions, emphasizing the timing and control of system pins like CLK and WR. It also provides a detailed I/O correspondence table for the boundary scan register pins.
Application Notes & White Papers (3)
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