Overview
Description
When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
Features
- High-Speed Operation: tpd (D to Q) = 16ns typ (CL = 50pF)
- High Output Current: Fanout of 15 LSTTL Loads
- Wide Operating Voltage: VCC = 2V to 6V
- Low Input Current: 1µA max
- Low Quiescent Supply Current: ICC (static) = 4µA max (Ta = 25°C)
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Support
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