Features
- PCIe Gen5 phase jitter < 50fs rms
- PCIe Gen6 phase jitter < 40fs rms
- 3.3V operation
- Three 100MHz dedicated output pairs with individual OE# pins
- Two MXCLK output pairs multiplexable between 100MHz and 25MHz
- One 25MHz dedicated output pair
- 85Ω differential Low-Power HCSL (LP-HCSL) outputs eliminate 24 resistors, saving 39mm2 of area
- Three selectable SMBus addresses
- Supports 0%, -0.3% and -0.5% spread-spectrum amounts
- Side-Band Interface allows real-time hardware control of all output enables
- 5 × 5 mm, 40-VFQFPN
- -40°C to +85°C operating temperature range
9SQ445 - Block Diagram
Description
The 9SQ445 is a CK440Q Lite clock synthesizer for newer Intel-based server platforms. The 9SQ445 is a single-chip, PCIe Gen6 compliant device. It is designed to work as a complete clock solution, or in combination, with DB2000Q-compliant or other clock buffers to provide point-to-point clocks to multiple receiving agents.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 6 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Inputs | 1 |
| Power Consumption Typ (mW) | 400 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Xtal Freq (MHz) | 25 - 25 |
| Diff. Termination Resistors | 0 |
| Package Area (mm²) | 64 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Function | Generator |
| Product Category | PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 40 | 0.4 |
| Part Number | Status | Samples | Longevity | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9SQ445NDGI | Active | Available | 2040 Apr | Out of Stock | VFQFPN | 40# | Tray | 3 | 0 | 490# | Yes | e3 Sn | -40 to 85°C |
| 9SQ445NDGI8 | Active | N/A | 2040 Apr | Out of Stock | VFQFPN | 40# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C |
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- Application NoteAI-generated Summary: Crystal layout and routing require 60Ω non-coupled traces routed through load capacitor pads to minimize stray capacitance. The crystal, load capacitors, and traces must be isolated from other nets and placed over a continuous ground plane without splits. Test points should have high impedance and low capacitance, with minimal use of vias. Load capacitor grounds should connect to the XtalGND pin to reduce noise. Crystal load capacitors work in series, and their values must consider stray capacitance to achieve the target load capacitance. Crystal drive power depends on frequency, ESR, total capacitance, and amplifier gain, with power increasing nonlinearly with capacitance and ESR. Validation of REFCLK frequency is essential during board design.
- White PaperPDF 1.35 MB 7WDXRDKU4E7E-6-61930 Aug 05, 2020As PCIe data rates increase and jitter budgets tighten, accurately measuring reference clock jitter becomes more challenging. This paper examines how intrinsic jitter in test setups impacts measurement accuracy and compares results from Phase Noise Analyzers and digital sampling oscilloscopes. It also explores methods to isolate and correct for intrinsic jitter using noiseless PCIe Gen5 clock sources and real-world components such as fan-out buffers and clock generators.
- Application NotePDF 235 KB 7WDXRDKU4E7E-5-58851 Apr 08, 2015
- Application NotePDF 115 KB 7WDXRDKU4E7E-5-57294 May 07, 2014
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NoteAI-generated Summary: Crystal layout and routing require 60Ω non-coupled traces routed through load capacitor pads to minimize stray capacitance. The crystal, load capacitors, and traces must be isolated from other nets and placed over a continuous ground plane without splits. Test points should have high impedance and low capacitance, with minimal use of vias. Load capacitor grounds should connect to the XtalGND pin to reduce noise. Crystal load capacitors work in series, and their values must consider stray capacitance to achieve the target load capacitance. Crystal drive power depends on frequency, ESR, total capacitance, and amplifier gain, with power increasing nonlinearly with capacitance and ESR. Validation of REFCLK frequency is essential during board design.
- White PaperPDF 1.35 MB 7WDXRDKU4E7E-6-61930 Aug 05, 2020As PCIe data rates increase and jitter budgets tighten, accurately measuring reference clock jitter becomes more challenging. This paper examines how intrinsic jitter in test setups impacts measurement accuracy and compares results from Phase Noise Analyzers and digital sampling oscilloscopes. It also explores methods to isolate and correct for intrinsic jitter using noiseless PCIe Gen5 clock sources and real-world components such as fan-out buffers and clock generators.View More (10)
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This video compares PCIe Gen3–7 common clock jitter filters with a typical 12kHz to 20MHz plot to highlight the differences in filtering approaches.
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Hi all,We are redesigning project right now we need alternate for 5P49V5933B000LTGI this component. I am kindly requesting you to share the details with unit price, lead time, ROHS status, and reference design
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