Features
- PCIe Gen5 phase jitter < 50fs rms
- PCIe Gen6 phase jitter < 40fs rms
- 3.3V operation
- Three 100MHz dedicated output pairs with individual OE# pins
- Two MXCLK output pairs multiplexable between 100MHz and 25MHz
- One 25MHz dedicated output pair
- 85Ω differential Low-Power HCSL (LP-HCSL) outputs eliminate 24 resistors, saving 39mm2 of area
- Three selectable SMBus addresses
- Supports 0%, -0.3% and -0.5% spread-spectrum amounts
- Side-Band Interface allows real-time hardware control of all output enables
- 5 × 5 mm, 40-VFQFPN
- -40°C to +85°C operating temperature range
Description
The 9SQ445 is a CK440Q Lite clock synthesizer for newer Intel-based server platforms. The 9SQ445 is a single-chip, PCIe Gen6 compliant device. It is designed to work as a complete clock solution, or in combination, with DB2000Q-compliant or other clock buffers to provide point-to-point clocks to multiple receiving agents.
Parameters
Attributes | Value |
---|---|
Function | Generator |
Architecture | Common, SRIS, SRNS |
App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6 |
Diff. Outputs | 6 |
Diff. Output Signaling | LP-HCSL |
Output Impedance | 85 |
Diff. Inputs | 1 |
Power Consumption Typ (mW) | 400 |
Supply Voltage (V) | 3.3 - 3.3 |
Advanced Features | 25MHz output(s), 100MHz output(s), Spread Spectrum, PFT |
Package Options
Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
---|---|---|---|
VFQFPN | 5.0 x 5.0 x 0.9 | 40 | 0.4 |
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Sample Code
Simulation Models
A brief comparison of PCI Express (PCIe) Gen3-7 common clock jitter filters vs. a typical 12k to 20MHz plot. Presented by Ron Wade, System Architect at Renesas.
For more information, visit the PCI Express Clocks page.
News & Blog Posts
Blog Post
Apr 14, 2022
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Blog Post
Mar 29, 2022
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News
Feb 4, 2021
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Blog Post
May 22, 2018
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News
Apr 30, 2018
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