Features
- PCIe Gen7 phase jitter < 18fs rms
- 3 x 25MHz dedicated output pairs
- 7 x 100MHz dedicated output pairs with individual OE# pins
- 9 MXCLK output pairs multiplexable between 100MHz and 25MHz
- 3.3V operation
- 85Ω differential Low-Power HCSL (LP-HCSL) outputs eliminate 80 resistors, saving 130mm2 of area
- 9 selectable SMBus addresses
- Supports 0%, -0.3% and -0.5% spread-spectrum amounts
- Side-Band Interface allows real-time hardware control of all output enables
- OE# pin control of 100M[6:0] supports PCIe slot CLKREQ#
- Dedicated Platform Time input and output clocks (PFT_IN and PFT_OUT)
- 8 × 8 mm dual-row 100-VFQFPN
- -40°C to +85°C operating temperature range
9SQ440 - Block Diagram
Description
The 9SQ440 is an Intel CK440 main clock synthesizer for Intel cloud and HPC platforms, and newer Intel-based server platforms. 9SQ440 is a single-chip, PCIe Gen6 compliant, and is designed to work as a complete clock solution or in combination with DB2000Q-compliant clock buffers to provide point-to-point clocks to multiple receiving agents.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 20 |
| Diff. Output Signaling | LP-HCSL |
| Power Consumption Typ (mW) | 875 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Xtal Freq (MHz) | 25 - 25 |
| Diff. Termination Resistors | 0 |
| Package Area (mm²) | 64 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Function | Generator |
| Product Category | PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 8.0 x 8.0 x 0.55 | 100 | 0.5 |
| Part Number | Status | Samples | Longevity | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9SQ440NQQI | Active | Available | 2040 Apr | Out of Stock | VFQFPN | 1ku | $5 | 100# | Tray | 3 | 0 | 260# | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
| 9SQ440NQQI8 | Active | N/A | 2040 Apr | Out of Stock | VFQFPN | 1ku | $5 | 100# | Reel | 3 | 3000# | 0 | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
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- Datasheet9SQ440 DatasheetRECOMMENDED
- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- Application NoteAI-generated Summary: Crystal layout and routing require 60Ω non-coupled traces routed through load capacitor pads to minimize stray capacitance. The crystal, load capacitors, and traces must be isolated from other nets and placed over a continuous ground plane without splits. Test points should have high impedance and low capacitance, with minimal use of vias. Load capacitor grounds should connect to the XtalGND pin to reduce noise. Crystal load capacitors work in series, and their values must consider stray capacitance to achieve the target load capacitance. Crystal drive power depends on frequency, ESR, total capacitance, and amplifier gain, with power increasing nonlinearly with capacitance and ESR. Validation of REFCLK frequency is essential during board design.
- Application NoteAI-generated Summary: The document details solder paste stencil design guidelines for the NQQ100 dual-row VFQFPN package used in the 9SQ440NQQ device. It specifies PCB pad dimensions based on the NSMD pattern, stencil aperture sizes with a 1:1 ratio for peripheral pins and 60-80% opening for the center pad arranged in a 2x2 matrix. Stencil thickness ranges from 100 to 125 μm. It recommends laser-cut electro-polished or electroformed trapezoidal stencils. VIA placement in the PCB thermal pad is also addressed, with diagrams included. Revision history notes VIA placement diagrams and updated package outline links.
- White PaperPDF 1.35 MB 7WDXRDKU4E7E-6-61930 Aug 05, 2020As PCIe data rates increase and jitter budgets tighten, accurately measuring reference clock jitter becomes more challenging. This paper examines how intrinsic jitter in test setups impacts measurement accuracy and compares results from Phase Noise Analyzers and digital sampling oscilloscopes. It also explores methods to isolate and correct for intrinsic jitter using noiseless PCIe Gen5 clock sources and real-world components such as fan-out buffers and clock generators.
- Application NotePDF 235 KB 7WDXRDKU4E7E-5-58851 Apr 08, 2015
- Application NotePDF 115 KB 7WDXRDKU4E7E-5-57294 May 07, 2014
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Datasheet9SQ440 DatasheetRECOMMENDED
Recommended Documents (1)
- Datasheet9SQ440 DatasheetRECOMMENDED
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NoteAI-generated Summary: Crystal layout and routing require 60Ω non-coupled traces routed through load capacitor pads to minimize stray capacitance. The crystal, load capacitors, and traces must be isolated from other nets and placed over a continuous ground plane without splits. Test points should have high impedance and low capacitance, with minimal use of vias. Load capacitor grounds should connect to the XtalGND pin to reduce noise. Crystal load capacitors work in series, and their values must consider stray capacitance to achieve the target load capacitance. Crystal drive power depends on frequency, ESR, total capacitance, and amplifier gain, with power increasing nonlinearly with capacitance and ESR. Validation of REFCLK frequency is essential during board design.
- Application NoteAI-generated Summary: The document details solder paste stencil design guidelines for the NQQ100 dual-row VFQFPN package used in the 9SQ440NQQ device. It specifies PCB pad dimensions based on the NSMD pattern, stencil aperture sizes with a 1:1 ratio for peripheral pins and 60-80% opening for the center pad arranged in a 2x2 matrix. Stencil thickness ranges from 100 to 125 μm. It recommends laser-cut electro-polished or electroformed trapezoidal stencils. VIA placement in the PCB thermal pad is also addressed, with diagrams included. Revision history notes VIA placement diagrams and updated package outline links.View More (11)
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This video compares PCIe Gen3–7 common clock jitter filters with a typical 12kHz to 20MHz plot to highlight the differences in filtering approaches.
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