Features
- PCIe Gen6 additive phase jitter: 4fs RMS
- PCIe Gen7 additive phase jitter: 2.8fs RMS
- DB2000Q/DB1206 additive phase jitter: 12fs RMS
- 12kHz–20MHz additive phase jitter: 36fs RMS at 156.25MHz
- Power-down tolerant (PDT) inputs
- Flexible startup sequencing (FSS)
- SMBus-enabled automatic clock parking (ACP)
- CLKIN accepts HCSL or LVDS signal levels
- 12 LP-HCSL outputs with 85Ω impedance
Description
The 9QXL1200 is an ultra-high performance PCIe Gen7 fanout buffer that is backward compatible with earlier PCIe generations. It features a loss-of-signal (LOS) output for system monitoring and resiliency. The device also incorporates power-down tolerant (PDT) and flexible startup sequencing (FSS) capabilities, simplifying system design.
Parameters
| Attributes | Value |
|---|---|
| Temp. Range (°C) | -40 to 105°C |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| LGA | 5.0 x 5.0 x 0.66 | 64 | 0.5 |
Product Comparison
| 9QXL1200 | 9QXL2001C | |
| Core Voltage (V) | 3.3 | 3.3 |
| Output Impedance | 85 | 85 |
| App Jitter Compliance | DB1206, DB2000Q, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7, QPI, UPI | 25G EDR, DB2000Q, IF-UPI, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, QPI, UPI |
| VOUT Slew-rate Control | Yes | No |
| Additive Jitter | 4fs | 4fs |
Applications
- Cloud and high-performance computing
- NVMe storage
- Networking
- AI accelerators
Applied Filters:
Filters
Software & Tools
Sample Code
Simulation Models
The RC family consists of PCIe Gen7 clock buffer and multiplexer solutions, providing the industry's smallest and most compact footprint.
A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
This video compares PCIe Gen3–7 common clock jitter filters with a typical 12kHz to 20MHz plot to highlight the differences in filtering approaches.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT. For more information about IDT's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information, visit Renesas's PCIe Timing Solutions page.