Features
- LP-HCSL output with integrated terminations; saves four resistors compared to standard HCSL output
- 1.8V operation; 12mW typical power consumption
- Selectable asynchronous or glitch-free switching; allows the mux to be selected at power up even if both inputs are not running, then transition to glitch-free switching mode
- Spread spectrum compatible; supports EMI reduction
- OE# pin; supports DIF power management
- HCSL differential inputs; can be driven by common clock sources
- 1MHz to 200MHz operating frequency
- Configuration can be accomplished with strapping pins; SMBus interface is not required for device control
- Space-saving 3mm x 3mm 16-VFQFPN; minimal board space
Description
The 9DMV0141 is a 1.8V very-low power PCIe Gen 1–5 clock mux. The device has integrated output terminations for direct connection to 100Ω transmission lines. The output has an OE# pin for optimal system control and power management. The parts provide asynchronous or glitch-free switching modes.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 1 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 200 |
| Diff. Inputs | 2 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 12, 14 |
| Supply Voltage (V) | 1.8 - 1.8 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 0 |
| Package Area (mm²) | 9 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 2 |
| Input Freq (MHz) | 1 - 200 |
| Additive Phase Jitter Typ RMS (fs) | 300 |
| Function | Multiplexer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 1.8 |
| Output Voltage (V) | 0.8 |
| Product Category | Clock Multiplexers, PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 16 | 0.5 |
Applications
- Servers
- nVME drives
- Embedded systems/Industrial control
- High-performance computing
- Accelerators
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Power Consumption Typ (mW) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DMV0141AKILF | Active | Available | In Stock | VFQFPN | 1ku | $1.45 | 16# | Tray | 3 | 14mW | 0 | 624# | Yes | e3 Sn | -40 to 85°C | MALAYSIA | TAIWAN |
| 9DMV0141AKILFT | Active | N/A | In Stock | VFQFPN | 1ku | $1.45 | 16# | Reel | 3 | 14mW | 2500# | 0 | Yes | e3 Sn | -40 to 85°C | MALAYSIA | TAIWAN |
| 9DMV0141BKILF | Active | Available | Out of Stock | VFQFPN | 1ku | $1.68 | 16# | Tray | 3 | 12mW | 0 | 624# | Yes | e3 Sn | -40 to 85°C | MALAYSIA | TAIWAN |
| 9DMV0141BKILFT | Active | N/A | In Stock | VFQFPN | 1ku | $1.68 | 16# | Reel | 3 | 12mW | 2500# | 0 | Yes | e3 Sn | -40 to 85°C | MALAYSIA | TAIWAN |
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014View More (9)
Application Notes & White Papers (9)
- Product Change NoticePDF 734 KB Nov 16, 2022
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- Product BriefPDF 378 KB 7WDXRDKU4E7E-6-1169 Aug 14, 2012
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A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
IDT (acquired by Renesas) engineer provides a brief tutorial describing the main differences between standard HCSL and low-power HCSL (LP-HCSL).
Presented by Ron Wade, PCI Express timing expert.
An overview of IDT's full-featured PCI Express (PCIe) clock multiplexers addressing PCIe Gen 1, Gen 2, Gen 3, and Gen 4.
Presented by Ron Wade, PCI Express clock expert at IDT.
An overview of PCI Express applications and how IDT's industry-leading portfolio of PCIe clock products addresses the requirements. The video briefly discusses PCIe riser cards, embedded SOC, and PCIe storage (NVME) examples.
Presented by Ron Wade, System Architect at IDT.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas).
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
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