Features
- Four low-power differential output pairs
- Individual OE# control of each output pair
- Output cycle-cycle jitter < 25ps additive
- Output-to-output skew: < 50ps
- Low-power differential fanout buffer for PCI Express and CPU clocks
- Available in commercial (0 °C to +70 °C) and industrial (-40 °C to +85 °C) temperature ranges
- Available in 20-VFQFPN or 20-TSSOP packages
9DBL411B - Block Diagram
Description
The 9DBL411 is a four-output lower power differential buffer. Each output has its own OE# pin. The device has a maximum operating frequency of 150MHz.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 4 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 15 - 150 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 132 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 8 |
| Package Area (mm²) | 28.6 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 15 - 150 |
| Additive Phase Jitter Typ RMS (fs) | 40 |
| Function | Fanout Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 0.8 |
| Product Category | PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TSSOP | 6.5 x 4.4 x 1.0 | 20 | 0.65 |
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Package Area (mm²) | Pitch (mm) | Pkg. Dimensions (mm) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DBL411BGILF | Active | Available | In Stock | TSSOP | 1ku | $1.61 | 20# | Tube | 1 | 0 | 74# | 28.6mm² | 0.65mm | 6.5 x 4.4 x 1.0 | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
| 9DBL411BGILFT | Active | N/A | In Stock | TSSOP | 1ku | $1.61 | 20# | Reel | 1 | 3000# | 0 | 28.6mm² | 0.65mm | 6.5 x 4.4 x 1.0 | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
| 9DBL411BGLF | Active | Available | In Stock | TSSOP | 1ku | $1.45 | 20# | Tube | 1 | 0 | 74# | 28.6mm² | 0.65mm | 6.5 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C | TAIWAN | SINGAPORE |
| 9DBL411BGLFT | Active | N/A | In Stock | TSSOP | 1ku | $1.45 | 20# | Reel | 1 | 3000# | 0 | 28.6mm² | 0.65mm | 6.5 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C | TAIWAN | SINGAPORE |
| 9DBL411BKILF | NRND | N/A | In Stock | VFQFPN | 1ku | $1.46 | 20# | Tray | 1 | 0 | 490# | 16mm² | 0.5mm | 4.0 x 4.0 x 1.0 | Yes | e3 Sn | -40 to 85°C | MALAYSIA | SINGAPORE |
| 9DBL411BKILFT | NRND | N/A | In Stock | VFQFPN | 1ku | $1.46 | 20# | Reel | 1 | 2500# | 0 | 16mm² | 0.5mm | 4.0 x 4.0 x 1.0 | Yes | e3 Sn | -40 to 85°C | MALAYSIA | SINGAPORE |
| 9DBL411BKLF | NRND | N/A | Out of Stock | VFQFPN | 1ku | $1.35 | 20# | Tray | 1 | 0 | 490# | 16mm² | 0.5mm | 4.0 x 4.0 x 1.0 | Yes | e3 Sn | 0 to 70°C | MALAYSIA | SINGAPORE |
| 9DBL411BKLFT | NRND | N/A | In Stock | VFQFPN | 1ku | $1.35 | 20# | Reel | 1 | 2500# | 0 | 16mm² | 0.5mm | 4.0 x 4.0 x 1.0 | Yes | e3 Sn | 0 to 70°C | MALAYSIA | SINGAPORE |
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
IDT (acquired by Renesas) engineer provides a brief tutorial describing the main differences between standard HCSL and low-power HCSL (LP-HCSL).
Presented by Ron Wade, PCI Express timing expert.
Support Communities
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Do the differential input and output of 9DBL411BGLFT require AC coupling capacitors?
Dear Renesas Team, I'm using a 9DBL411BGLFT chip to convert one PCIe CLK signal into four PCIe CLK signals. The PCIe CLK is PCIe 3.0, 100MHz, and comes from the PCIe CLK output pin of an Intel N100 processor. The four branched PCIe CLK signals are all used ...
Jul 6, 2025
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