Features
- Two 0.7V current mode differential HCSL output pairs
- One differential clock input
- CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Maximum output frequency: 140MHz
- Input frequency range: 90MHz - 140MHz
- VCO range: 450MHz - 700MHz
- Output skew: 110ps (maximum)
- Cycle-to-cycle jitter: 110ps (maximum)
- RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.42ps (typical)
- 3.3V operating supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free RoHS compliant package
- Industrial temperature information available upon request
Description
The 9DB202 is a high performance 1-to-2 Differential-to-HCSL Jitter Attenuator designed for use in PCI Express®™ systems. In some PCI Express®™ systems, such as those found in desktop PCs, the PCI Express®™ clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter-attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This setting offers the best jitter attenuation and is still high enough to pass a triangular input spread spectrum profile. In high bandwidth mode, the PLL bandwidth is at 1MHz and allows the PLL to pass more spread spectrum modulation. For serdes which have x10 reference multipliers instead of x12.5 multipliers, each of the two PCI Express®™ outputs (PCIEX0:1) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1).
Support Communities
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PCIe Clock Frequency Translator and Jitter Reducer
Hi, We'ree looking for a device to replace an obsolete PCIe Clock jitter reducer and Frequency Translator on a PC plug-in card. The basic functions we need are:- a) Accept 100 MHz HCSL reference clock as input.b) Generate a 125 MHz HCSL reference clock as output.c ...
Mar 19, 2026
Knowledge Base
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When using the 9DB202 in PLL mode, why do we see a 80 MHz signal on the output, even when there is no input provided?
When the device is in PLL mode, the VCO is always running. There is no VCO shutdown pin on the part. If there is no reference input being supplied, the PLL reference is 0 Hz. The negative feedback loop then drives the VCO control pin until the VCO frequency is ...
Oct 31, 2016
Support Communities
