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93722

Obsolete

DDR Zero Delay Clock Buffer

Overview

DDR Zero Delay Clock Buffer

  • Low skew, low jitter PLL clock driver
  • I2C for functional and output control
  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • 3.3V tolerant CLK_INT input

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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Diagram of ECAD Models

Models
Type Title Date
Model - IBIS
93722 IBIS Model
ZIP 7 KB
1 item

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Support Communities

  1. SLG46108 DC Powerline Communication for longer wires

    Dear support, I found your application note AN-CM-318 very useful. https://www.dialog-semiconductor.com/sites/default/files/2021-09/AN-CM-… I rebuild it and it works for short wire connections. I would be interested if it could also work ...

    Apr 5, 2022