Features
- 0.3ps RMS typical jitter (including spurs), 12kHz to 20MHz
- Operating modes: locked to input signal and free-run
- Digitally Controlled Oscillator (DCO) mode for software adjustment of operating frequency
- Operates from a 10MHz to 40MHz fundamental-mode crystal
- Accepts one LVPECL, LVDS, LVHSTL, HCSL, or LVCMOS input clock
- Accepts frequencies ranging from 10MHz up to 600MHz
- Clock input monitoring
- Generates 12 LVPEC/LVDS/HCSL or 24 LVCMOS output clocks
- Output frequencies ranging from 8kHz up to 1.0GHz (diff)
- Output frequencies ranging from 8kHz up to 250MHz (LVCMOS)
- Two Output Enable control inputs
- Lock and Loss-of-Signal status outputs
- Programmable output de-skew adjustments in steps as small as 16ps
- Register programmable through I²C or via external I²C EEPROM
- Bypass clock paths and reference output for system tests
- -40 °C to +85 °C ambient operating temperature
- Packaged in a 72-pin QFN, lead-free RoHS (6)
- Supported by Renesas' Timing Commander Software
Description
The 8T49N1012 has one fractional-feedback PLL that can be used for frequency synthesis. It is equipped with two integer and eight fractional output dividers, allowing the generation of up to ten different output frequencies, ranging from 8kHz to 1GHz. Eight of these frequencies are completely independent of each other and the inputs. Two more are related frequencies. The twelve outputs may select among LVPECL, LVDS, HSCL, or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency synthesis application, including 1G, 10G, 40G, and 100G Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates. The device supports Output Enable inputs and Lock and LOS status outputs.
Try the Custom Part Configuration Utility.
Applications
- OTN or SONET/SDH equipment line cards (up to OC-192, and supporting FEC ratios)
- Gigabit and Terabit IP switches/routers
- Wireless base station baseband
- Data communications
Try the Custom Part Configuration Utility.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 8T49N1012-998NLGI | Obsolete | N/A | In Stock | VFQFPN | 72# | Tray | 3 | 0 | 168# | Yes | e3 Sn | -40 to 85°C |
| 8T49N1012-998NLGI8 | Obsolete | N/A | Out of Stock | VFQFPN | 72# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C |
Filters
Applied Filters
- Application NotePDF 187 KB R31AN0065EU0101 Rev.1.01 Nov 14, 2023
- Application NotePDF 348 KB R31AN0040EU0100 Rev.1.00 Mar 10, 2023
- End Of Life NoticePDF 1.22 MB Sep 07, 2022
- End Of Life NoticePDF 1.15 MB Aug 15, 2022
- Application NotePDF 157 KB R31AN0020EU0100 Rev.1.00 May 16, 2022AI-generated Summary: EEPROM read errors on UFT3G devices occur when the SDA line's rising edge is slowed beyond 136ns due to extra loading from devices like LEDs or I2C extenders. To ensure reliable EEPROM access, adjust the pull-up resistor on the SDA line so the voltage rises from 0 to 1.8V in less than 136ns, while maintaining a low enough voltage (below 0.4V) when driven low. A 1kΩ pull-up resistor is a recommended starting point. These guidelines optimize I2C bus performance and prevent EEPROM read halts.
- Application NotePDF 415 KB Jul 17, 2020AI-generated Summary: Timing considerations are critical when writing to UFT3G devices via I2C or SPI, especially regarding idle times between writes to ensure successful communication. Single-byte and block write sequences are supported, with specific idle time recommendations depending on whether PLL feedback dividers or DSM_ORD registers are modified. Calibration times vary based on crystal frequency and DLCNT settings. System implementation guidelines include disabling/enabling DPLL calibration and managing I2C wait times to avoid data corruption during frequency recalibration.
- Product Change NoticePDF 163 KB May 20, 2020
- Application Note
- Application NotePDF 301 KB 7WDXRDKU4E7E-5-57382 Jun 05, 2014
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
Recommended Documents (1)
Datasheets (1)
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- Application NotePDF 187 KB R31AN0065EU0101 Rev.1.01 Nov 14, 2023
- Application NotePDF 348 KB R31AN0040EU0100 Rev.1.00 Mar 10, 2023
- Application NotePDF 157 KB R31AN0020EU0100 Rev.1.00 May 16, 2022AI-generated Summary: EEPROM read errors on UFT3G devices occur when the SDA line's rising edge is slowed beyond 136ns due to extra loading from devices like LEDs or I2C extenders. To ensure reliable EEPROM access, adjust the pull-up resistor on the SDA line so the voltage rises from 0 to 1.8V in less than 136ns, while maintaining a low enough voltage (below 0.4V) when driven low. A 1kΩ pull-up resistor is a recommended starting point. These guidelines optimize I2C bus performance and prevent EEPROM read halts.
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022View More (27)
Application Notes & White Papers (27)
- End Of Life NoticePDF 1.22 MB Sep 07, 2022
- End Of Life NoticePDF 1.15 MB Aug 15, 2022
- Product Change NoticePDF 163 KB May 20, 2020
- Product Change NoticePDF 983 KB Jun 25, 2019
- Product Change NoticePDF 454 KB Feb 08, 2019View More (7)
Product Notices (PCN, EOL, etc) (7)
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Schematics & Design Files (1)
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- OverviewPDF 1.62 MB R31DS0106EU0000-7WDXRDKU4E7E-6-9407 Rev.0.00 Dec 16, 2021
- Product BriefPDF 631 KB 7WDXRDKU4E7E-6-11303 May 02, 2016
Marketing Collateral (2)
- Technical BriefPDF 238 KB 7WDXRDKU4E7E-6-11137 Feb 08, 2016
Other (1)
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Renesas Boards & Kits
Evaluation Kit for 8T49N1012
The EVK-8T49N1012 evaluation board kit is a platform that is designed to help the customer evaluate Renesas's 8T49N1012 FemtoClockR NG 12-output Frequency Synthesizer. When the board is connected to a PC running Renesas' Timing CommanderTM software through USB, the device can be configured and... Read More