Features
- Three Differential LVDS output pairs
- One Differential clock input
- CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Output frequency range: 98MHz - 320MHz
- Input frequency range: 98MHz - 128MHz
- VCO range: 490MHz - 640MHz
- Cycle-to-cycle jitter: 35ps (maximum)
- Supports PCI Express® Spread-Spectrum Clocking
- The 2.1MHz bandwidth mode allows the system designer to make jitter attenuation/tracking skew design trade-offs
- 3.3V operating supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
Description
The 874003D-02 is a high performance Differential- to-LVDS Jitter Attenuator designed for use in PCI Express® systems. In some PCI Express® systems, such as those found in desktop PCs, the PCI Express® clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874003D-02 has a bandwidth of 2.1MHz. The 2.1MHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 874003D-02 uses IDT's 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express® add-in cards.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Temp. Grade | Pb (Lead) Free | Carrier Type |
|---|---|---|---|---|---|---|---|---|
| 874003DG-02LF | Obsolete | N/A | Out of Stock | TSSOP | 20# | C | Yes | Tube |
| 874003DG-02LFT | Obsolete | N/A | Out of Stock | TSSOP | 20# | C | Yes | Reel |
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- End Of Life NoticePDF 161 KB 7WDXRDKU4E7E-5-59976 Mar 07, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
- Product Change NoticePDF 544 KB 7WDXRDKU4E7E-5-59710 Nov 13, 2015
- Product Change NoticePDF 95 KB 7WDXRDKU4E7E-5-59609 Oct 22, 2015
- Product Change NoticePDF 50 KB 7WDXRDKU4E7E-5-59245 Jul 21, 2015
Recommended Documents (1)
Datasheets (1)
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- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- End Of Life NoticePDF 161 KB 7WDXRDKU4E7E-5-59976 Mar 07, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
- Product Change NoticePDF 544 KB 7WDXRDKU4E7E-5-59710 Nov 13, 2015View More (7)
Product Notices (PCN, EOL, etc) (7)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.