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4:4 Differential-to-LVPECL/LVDS Clock Multiplexer

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG24
Lead Count (#):24
Pkg. Dimensions (mm):7.8 x 4.4 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)24
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)62
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Additive Phase Jitter Typ RMS (fs)220
Additive Phase Jitter Typ RMS (ps)0.22
Adjustable PhaseNo
Advanced FeaturesUniversal outputs
Channels (#)1
Core Voltage (V)2.5V, 3.3V
FunctionBuffer, Multiplexer
Input Freq (MHz)3000
Input TypeCML, LVDS, LVPECL
Inputs (#)4
Length (mm)7.8
MOQ62
Output Banks (#)1
Output Freq Range (MHz)3000
Output Skew (ps)25
Output TypeLVDS, LVPECL
Output Voltage (V)2.5V, 3.3V
Outputs (#)4
Package Area (mm²)34.3
Pitch (mm)0.65
Pkg. Dimensions (mm)7.8 x 4.4 x 1.0
Pkg. TypeTSSOP
Product CategoryClock Buffers & Drivers, Clock Multiplexers, RF Buffers
Prog. InterfacePin select
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)2.5 - 2.5, 3.3 - 3.3
Tape & ReelNo
Thickness (mm)1
Width (mm)4.4

Description

The 859S0424I is a 4:4 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The outputs for this device can either be programmed to give LVPECL or LVDS levels. The 859S0424I has four selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.