Overview
Description
The 859S0424I is a 4:4 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The outputs for this device can either be programmed to give LVPECL or LVDS levels. The 859S0424I has four selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.
Features
- High speed 4:1 differential multiplexer with a 1:4 fanout buffer
- Four programmable differential LVPECL or LVDS output pairs
- Four selectable differential PCLKx, nPCLKx input pairs
- PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML
- Maximum output frequency: 3GHz
- Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx inputs
- Part-to-part skew: 100ps (maximum)
- Propagation delay: 555ps (typical) @ 3.3V
- Additive phase jitter, RMS: 0.22ps (typical) @ 3.3V
- Full 3.3V or 2.5V supply modes
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
Comparison
Applications
Design & Development
Product Options
Applied Filters:
Support
Support Communities
Get quick technical support online from Renesas Engineering Community technical staff.
Support Communities
-
VCC_TAP pin
Hello, Is it okay to power the VCC_TAP pin in any other way that is not mentioned in the datasheets of 859S0212I, 859S0412I and 859S0424I multiplexer ICs ? Regards
Mar 20, 2024
FAQs
-
Is it okay to power the VCC_TAP pin in any other way that is not mentioned in the datasheets of 859S0212I, 859S0412I and 859S0424I multiplexer IC's ?
The table 3A in the datasheet mentions how to power the VCC_TAP pin. The conditions specified in the table have to always be meet in order for the part to work correctly. Therefore, there are no combinations a user should use besides what is specified in the table. The ...
Oct 31, 2016