Features
- Two differential LVHSTL compatible outputs
- One differential CLK, nCLK input pair
- CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
- Maximum output frequency: 700MHz
- Translates any single-ended input signal to LVHSTL levels with resistor bias on nCLK input
- Output skew: 30ps (maximum)
- Part-to-part skew: 250ps (maximum)
- Propagation delay: 1ns (maximum)
- Output duty cycle: 49% - 51% up to 266.6MHz
- VOH = 1.2V (maximum)
- 3.3V operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free RoHS compliant package
85211I - Block Diagram
Description
The 85211I is a low skew, high performance 1-to-2 Differential-to-LVHSTL Fanout Buffer. The CLK, nCLK pair can accept most standard differential input levels. The 85211I is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 85211I ideal for those clock distribution applications demanding well-defined performance and repeatability. For optimal performance, terminate all outputs.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Temp. Grade | Pb (Lead) Free | Carrier Type |
|---|---|---|---|---|---|---|---|---|
| 85211AMILF | Obsolete | N/A | Out of Stock | SOIC | 8# | I | Yes | Tube |
| 85211AMILFT | Obsolete | N/A | Out of Stock | SOIC | 8# | I | Yes | Reel |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
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- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014View More (11)
Application Notes & White Papers (11)
- End Of Life NoticePDF 192 KB 7WDXRDKU4E7E-5-57646 Sep 04, 2014
- Product Change NoticePDF 439 KB 7WDXRDKU4E7E-5-56251 Oct 11, 2013
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
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