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7284

Obsolete

4K x 9 DualAsync FIFO, 5.0V

Overview

The 7284 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

7284 - Block Diagram
7284 - Block Diagram
  • Equivalent to two 7204 4K x 9 FIFOs
  • Asynchronous and simultaneous read and write
  • Status Flags: Empty, Half-Full, Full
  • Auto-retransmit capability
  • Available in 56 pin TSSOP
  • Industrial temperature range (–40C to +85C) is available

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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Diagram of ECAD Models

Models
Type Title Date
Model - SPICE
7284 HSPICE
Log in to Download TAR 32 KB
Model - IBIS
7284 IBIS
ZIP 11 KB
2 items

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Support Communities

  1. RZV2M ISP integration issue

    We have created a board based on the RZ/V2M processor. The only change we made compared to the RZV2M EVK is that we swapped the DDR data pins. We also made the necessary changes to the bootloader sources to accommodate these modifications. I am able to boot Linux ...

    Oct 5, 2024
  2. Need Help

    Hi guys, I am an Electronics Engineering student from Malaysia. I am very new to this microcontroller. I am having some difficulties in my final year project. I am using DA14580 to build an Ultra Low Power embedded system for ECG acquisition. I will be drawing the schematic design using ...

    Jan 22, 2017
  3. P24 bank pins configuration issue in RZ-FIVE

    Hello, We are configuring P24 bank pins for below interfaces and below is the dts configurations for the same. SCIF4:TX: P24_5 ALT5RX: P24_4 ALT5Below is the dts pinmux configuration: scif4_pins: scif4 { pinmux = , /* TxD */ Apr 12, 2023

View All Results from Support Communities (11)