Features
- High performance system speed - 100 MHz
- (7.5 ns Clock-to-Data Access)
- ZBT Feature - No dead cycles between write and read
- cycles
- Internally synchronized output buffer enable eliminates the need to control OE
- Single R/W (READ/WRITE) control pin
- 4-word burst capability (Interleaved or linear)
- Individual byte write (BW1 - BW4) control (May tie active)
- Three chip enables for simple depth expansion
- 3.3V power supply (±5%)
- 3.3V (±5%) I/O Supply (VDDQ)
- Power down controlled by ZZ input
- Available in 100-pin TQFP, 119-pin BGA and 165 fpBGA packages
Description
The 71V65903 3.3V CMOS SRAM is organized as 512K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65903 contain address, data-in and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.
Parameters
| Attributes | Value |
|---|---|
| Density (Kb) | 9216 |
| Bus Width (bits) | 18 |
| Core Voltage (V) | 3.3 |
| Pkg. Code | BQG165, PKG100 |
| Organization | 512K x 18 |
| I/O Voltage (V) | 2.5 - 2.5 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | ZBT |
| Output Type | Flowthrough |