Features
- 4 - low power differential output pairs
- Individual OE# control of each output pair
- Low power differential outputs
- Power down mode when all OE# are high
- Industrial temperature range
- 20-pin MLF
- Output cycle-cycle jitter <15 ps additive
- Output to Output skew: <50 ps
- PCIe Gen3 additive phase jitter <0.3 ps rms
- 10.3125G / 64 additive phase jitter <100 fs rms
6V31021 - Block Diagram
Description
The IDT6V31021 is a 4-output low- power differential buffer. Each output has its own OE# pin. It has a maximum operating frequency of 167 MHz and supports all SERDES clock frequencies for Freescale QorIQ CPUs.
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 6V31021NLGI | NRND | N/A | In Stock | VFQFPN | 1ku | $1.94 | 20# | Tray | 1 | 0 | 490# | Yes | e3 Sn | -40 to 85°C | MALAYSIA | SINGAPORE |
| 6V31021NLGI8 | NRND | N/A | In Stock | VFQFPN | 1ku | $1.94 | 20# | Reel | 1 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C | MALAYSIA | SINGAPORE |
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- Product Change NoticePDF 2.97 MB Dec 08, 2020
- Product Change NoticePDF 5.71 MB Jun 09, 2020
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 120 KB 7WDXRDKU4E7E-5-57289 May 06, 2014
- Application NotePDF 160 KB 7WDXRDKU4E7E-5-57287 May 06, 2014
- Product Change NoticePDF 5.61 MB Jan 08, 2020
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014View More (10)
Application Notes & White Papers (10)
- Product Change NoticePDF 2.97 MB Dec 08, 2020
- Product Change NoticePDF 5.71 MB Jun 09, 2020
- Product Change NoticePDF 5.61 MB Jan 08, 2020
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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