Features
- Supports PCI Express®TM HCSL Outputs 0.7V current mode differential pair
- Supports LVDS output Levels
- Packaged in 8-pin SOIC
- RoHS 5 (green) or RoHS 6 (green and lead-free) compliant packaging
- Operating voltage of 3.3V
- Low power consumption
- Input frequency of 25MHz
- Short-term jitter 100ps (peak-to-peak)
- Output Enable via pin selection
- Industrial temperature range available
- For PCIe Gen2 applications, see the 5V41064
- For PCIe Gen3 applications, see the 5V41234
557-01 - Block Diagram
Description
The 557-01 is a clock chip designed for use in PCI Express® cards as a clock source. It provides a pair of differential outputs at 100MHz in a small 8-pin SOIC package. Using Renesas' patented Phase-Locked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces HCSL (Host Clock Signal Level) differential outputs at 100MHz clock frequency. LVDS signal levels can also be supported via an alternative termination scheme.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 1 |
| App Jitter Compliance | PCIe Gen1 |
| Outputs (#) | 1 |
| Output Type | HCSL |
| Output Freq Range (MHz) | 100 - 100 |
| Input Freq (MHz) | 25 - 25 |
| Inputs (#) | 1 |
| Input Type | Crystal, LVCMOS |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 3.3 |
| Product Category | PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| SOIC | 4.9 x 3.9 x 1.5 | 8 | 1.27 |
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 557M-01LF | Active | Available | In Stock | SOIC | 1ku | $1.63 | 8# | Tube | 1 | 0 | 97# | Yes | e3 Sn | 0 to 70°C | THAILAND | SINGAPORE |
| 557M-01LFT | Active | N/A | Out of Stock | SOIC | 1ku | $1.63 | 8# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | 0 to 70°C | THAILAND | SINGAPORE |
| 557MI-01LF | Obsolete | N/A | Out of Stock | SOIC | 8# | Tube | 1 | 0 | 97# | Yes | e3 Sn | -40 to 85°C | |||
| 557MI-01LFT | Obsolete | N/A | Out of Stock | SOIC | 8# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | -40 to 85°C |
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More
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- End Of Life NoticePDF 218 KB 7WDXRDKU4E7E-5-62868 Apr 26, 2018
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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