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Low Skew Clock Inverter and Divider

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG16
Lead Count (#):16
Pkg. Dimensions (mm):5.0 x 4.4 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)16
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)96
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)0 to 70°C
Accepts Spread Spec InputNo
Advanced FeaturesReference Output
Clock Spec.T1, E1
Core Voltage (V)3.3V, 5V
Feedback InputNo
Input Freq (MHz)1.544 - 1.544, 2.048 - 2.048
Input TypeCrystal, LVCMOS
Inputs (#)4
Length (mm)5
MOQ192
Operating Freq24.704, 37.056, 32.768, 49.152
Output Banks (#)1
Output Freq Range (MHz)24.704 - 24.704, 37.056 - 37.056, 32.768 - 32.768, 49.152 - 49.152
Output TypeLVCMOS
Output Voltage (V)3.3V, 5V
Outputs (#)2
Package Area (mm²)22
Period Jitter Typ P-P (ps)100
Pitch (mm)0.65
Pkg. Dimensions (mm)5.0 x 4.4 x 1.0
Pkg. TypeTSSOP
Product CategoryGeneral Purpose Clocks
Prog. ClockNo
Reference OutputYes
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Spread SpectrumNo
Tape & ReelNo
Thickness (mm)1
Width (mm)4.4
Xtal Freq (KHz)1.54 - 1.54
Xtal Inputs (#)1

Description

The 548-05 is a low-cost, low-jitter, high-performance clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using Renesas’ patented analog/digital Phase-Locked Loop (PLL) techniques, the device uses a crystal or clock input to synthesize popular communications frequencies. Power down modes allow the chip to turn off completely, or the PLL and clock output to be turned off separately.