Overview
Description
The ISL5216EVAL1 evaluation board is used to evaluate the ISL5216 four-channel programmable digital downconverter.
The ISL5216 quad programmable digital downconverter (QPDC) is designed for high dynamic range applications such as cellular basestations where multiple channel processing is required in a small physical space. The QPDC combines into a single package a set of four channels which include: digital mixers, a quadrature carrier NCO, digital filters, a resampling filter, a cartesian to polar coordinate converter, and an automatic gain control (AGC) loop.
Features
- Up to 95MSPS input
- Four independently programmable downconverter channels in a single package
- Four parallel 17-bit inputs providing 16-bit fixed or one of several 17-bit floating point formats
- 32-bit programmable carrier NCO with >115dB SFDR
- 110dB FIR out of band attenuation
- Decimation from 4 to >65536
- 24-bit internal data path
- Digital AGC with up to 96dB of gain range
- Filter functions
- 1- to 5-stage CIC filter
- Half-band decimation and interpolation FIR filtering
- Programmable FIR filtering
- Resampling FIR filtering
- Cascadable filtering for additional bandwidth
- Four independent serial outputs
- 2.5V core, 3.3V I/O operation
- Pb-free plus anneal available (RoHS compliant)
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Datasheet | PDF 2.84 MB | |
| PCB Design Files | PDF 127 KB | |
| Application Note |
PDF
541 KB
AI-generated Summary:
The document details the IEEE Standard Test Access Port (TAP) and Boundary Scan Register configuration for the ISL5216. It explains the structure and operation of the 132-bit boundary scan register, including its shift register and parallel output register components. The boundary scan cells for input, output, and three-state pins enable observation and control of circuit pins during testing. The document outlines the behavior of the register in various TAP states and instructions, emphasizing the timing and control of system pins like CLK and WR. It also provides a detailed I/O correspondence table for the boundary scan register pins.
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Design & Development
Product Options
| Part Number | Status | Stock | Sampleable | Pb (Lead) Free |
|---|---|---|---|---|
| ISL5216EVAL1 | Obsolete | Out of Stock | N/A | No |
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