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RL78/G1H

Industry’s Lowest Power SubGHz wireless communication MCU

 

The RL78/G1H microcontroller supports IEEE802.15.4e/g and has industry’s lowest power consumption - min. 5.8 mA (3.3 V) at Stand-by mode in RF receipt. The balun circuit and filter circuit make the antenna circuit design easy. And it can be reduced external parts for cost reduction. It can be reduced CPU load and can be made easy development by built-in hardware functions for IEEE802.15.4e/g compliant especially Wi-SUN.

We also offer transceiver RAA604S00 conforming to IEEE802.15.4e/g that can be used in combination with microcontroller.  (The document is here.)

 

Key Features:

ITEM RL78/G1H 
Part Name R5F11FLJ R5F11FLK R5F11FLL
Memory Program Flash
256 KB 384 KB 512 KB
Data Flash 8 KB
SRAM 24 KB 32 KB 48 KB
CPU RL78 CPU Core
System Clock 32 MHz (max.)
Clock Circuit High-speed system clock

External main system clock input (EXCLK) 

1 - 20 MHz: VDD = 2.7 - 3.6 V, 

1 - 16 MHz: VDD = 2.4 - 3.6 V, 

1 - 8 MHz: VDD = 1.8 - 3.6 V

High Speed On-chip oscillator

1 MHz - 32 MHz (High speed main mode : 2.7 V - 3.6 V) 

1 MHz - 16 MHz (High speed main mode : 2.4 V - 3.6 V) 

1 MHz - 8 MHz (Low speed main mode : 1.8 V to 3.6 V)

Subsystem clock XT1 (Crystal) oscillation, External main system clock input (EXCLKS)  32.768 kHz (TYP.)
RF Reference clock 48 MHz (TYP.)
RF slow clock External clock input for RF block (EXSLK_RF) 32.768 kHz (TYP.)
Low Speed On-chip Oscillator 15 kHz (TYP.)
I/O port

Total 41 

(CMOS I/O : 26, CMOS input : 5, CMOS output : 1, 

N-ch O/D I/O : 4, GPIO (RF block) : 5)

SubGHz RF Transceivers Operating Frequency Band 863MHz - 928MHz
Modulation scheme / Data rate (kbps) 2FSK/GFSK : 10/20/40/50/100/150/200/300 4FSK/GFSK : 200/400
Quiescent current (RF portion) Vcc=3.3V, typ. RX:6.3mA, RX wait:5.8mA / TX:20mA(+10dBm)
Receiving sensitivity

-114dBm (GFSK 10Kbps, BER < 0.1% ) 

-105dBm (GFSK 100Kbps, BER < 0.1%)

Wireless circuit design support

Receiver balun and matching circuit

Transmitter balun and secondary/tertiary harmonic filter

PLL filter

VCO frequency auto-adjust function

Support IEEE802.15.4e/g

Dual Sub-GHz Communication filtering, Transmission frame auto-generation function,

*Preamble length: 4 – 1000 Bytes can be set, Auto ACK Reply / Reception function support

Timer 16-bit timer 9 channels, PWM output x 1
Watchdog timer 1 channel
Real-time clock (RTC) 1 channel
12-bit interval timer 1 channel
Clock output/buzzer output 2

- 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz 

(Main system clock: fMAIN = 20 MHz operation)

- 256 Hz, - 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz 

(Subsystem clock: fSUB = 32.768 kHz operation)

10-bit resolution A/D converter 6 channels
Serial interface CSI/UART 2 channel
CSI 1 channel (dedicated for internal communications)
I2C Bus 2 channel
Interrupt External : 7 
DTC 21 Factor
Voltage detector

Rising edge : 1.88 V - 3.13 V (10 stages) 

Falling edge : 1.84 V - 3.06 V (10 stages)

On-chip debug function Provided
Power supply voltage range 1.8 - 3.6 V
Operating ambient temperature TA = -40 ℃ to 85 ℃
Pin-Count 64-pins HVQFN 9 x 9 mm (0.5 mm pitch)

 

Pin Count / Memory Size Lineup:

Program Flash
SRAM
512KB
48KB
384KB
32KB
256KB
24KB
Pins
Package
64
HVQFN

 

Block Diagram:

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

 

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Software Design Support

Title Description
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E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)
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