特長
- LP-HCSL outputs eliminate 16 resistors; save 32mm2 of area
- PCIe Gen 1–5 compliance
- 4 OE# pins; SMBus control also available
- 3 selectable SMBus addresses
- 2 selectable ZDB bandwidths; minimizes jitter peaking in cascaded PLL topologies
- Hardware/SMBus control of ZDB bandwidth and fanout modes
- Spread spectrum compatible
- 100MHz ZDB mode
- 5mm × 5mm 32-VFQFPN package; small board footprint
説明
The 9ZXL0451E is a second-generation enhanced performance DB800ZL derivative for PCIe Gen 4 and 5 applications. In fanout (bypass) mode, it is DB2000Q compatible. A fixed external feedback in zero-delay buffers (ZDB) mode maintains low drift for critical QPI/UPI.
パラメータ
| 属性 | 値 |
|---|---|
| Diff. Outputs | 4 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 400 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 158 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 24 |
| Package Area (mm²) | 81 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 33 - 150 |
| Function | Zero Delay Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 0.7 |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 32 | 0.5 |
アプリケーション
- Servers/High-performance computing
- nVME storage
- Networking
- Accelerators
- Industrial control