Renesas Electronics Corporation
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MPC961P

Obsolete

Low Voltage Zero Delay Buffer

Overview

The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150ps the device meets the needs of the most demanding clock tree applications.

MPC961P - Block Diagram
MPC961P - Pinout
MPC961P - Block Diagram
MPC961P - Pinout
  • Fully Integrated PLL
  • Up to 200MHz I/O Frequency
  • LVCMOS Outputs
  • Outputs Disable in High Impedance
  • LVPECL Reference Clock Options
  • LQFP Packaging
  • ±50ps Cycle–Cycle Jitter
  • 150ps Output Skews

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

Explore ECAD Models
Diagram of ECAD Models

Models
Type Title Date
Model - IBIS
MPC961P IBIS Model
ZIP 20 KB
1 item

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